is42g32256 ETC-unknow, is42g32256 Datasheet - Page 7

• Manufacturer Part Number: is42g32256
• Description: 256k 16-mbit Synchronous Graphics
• Manufacturer: ETC-unknow

IS42G32256
Table 5. SGRAM vs SDRAM
Notes:
1. If DSF is low, SGRAM functionality is identical to SDRAM functionality.
2. SGRAM can be used as a unified memory by the appropriate DSF control; SGRAM = Graphic Memory + Main Memory.
Table 6. Mode Register Field Table to Program Modes
Register Programmed with MRS
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR037-0C
09/10/98
Special mode Register Programmed with SMRS
POWER UP SEQUENCE
1. Apply power and start clock, attempt to maintain DKE = “H” and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s.
3. Issue precharge commands for all banks of the devices.
4. Issue two or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Sequence of 4 and 5 may be changed.
The device is now ready for normal operation.
Notes:
1.
2.
3.
4.
A8 A7
A9
0
0
1
1
0
1
SDRAM Function
SGRAM Function
Address
Function
RFU (Reserved for Future Use) should stay “0” during MRS cycle.
If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
The full column burst (256-bit) is available only at Sequential mode of burst type.
If LC and LM both high (1), data of mask and color register will be unknown.
Function
Address
0
1
0
1
Write Burst Length
Test Mode
DSF
Mode Register Set
Single Bit
Length
Burst
Vendor
Type
Only
Use
RFU
A10
A10, A9, A8, A7
(1)
A6
MRS SMRS
X
0
0
0
0
1
1
1
1
L
W.B.L.
MRS
A5
CAS Latency
0
0
1
1
0
0
1
1
A9
H
(2)
A4
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
A6 Function
A8, A7
0 Disable
1 Enable
—
Load Color
2
3
TM
LC
A6
(4)
Write per bit
Bank Active
Disable
A3
0
1
with
Burst Type
L
Bank Active
CAS Latency
A6, A5, A4
Sequential
A5 Function
Interleave
0
1
Load Mask
Type
LM
A5
Disable
Enable
(4)
Write per bit
Bank Active
Enable
with
H
A2 A1 A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Burst Length
A3
BT
0
1
0
1
0
1
0
1 256(Full)
A4, A3, A2, A1, A0
Reserved
Reserved
Reserved
BT=0
Normal Block
Write
1
2
4
8
X
L
Burst Length
Write
A2, A1, A0
(3)
Write
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ISSI
H
BT=1
4
8
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