tc55vcm216astn40 TOSHIBA Semiconductor CORPORATION, tc55vcm216astn40 Datasheet

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... I/O5 I/O13 I/O6 I/O14 I/O7 DD TC55VCM216ASTN40,55 extreme temperature conditions. TC55VCM216ASTN Access Time 40 ns Access Time 40 ns Access Time 25 ns (Weight:0.35 g typ) A0~A17 Address Inputs CE , CE2 1 Chip Enable R/W Read/Write Control Output Enable Data Byte Control ...

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... A15 A17 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 CE 1 CE2 LB UB R/W OE MEMORY CELL ARRAY 2,048 × 128 × 16 (4,194,304) SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDRESS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR A16 CE TC55VCM216ASTN40, GND CE 2002-07-04 2/14 ...

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... RATING − − − − 40° to 85°C PARAMETER = 2.3 V~2 2.7 V~3 TC55VCM216ASTN40,55 I/O1~I/O8 I/O9~I/O16 Output Output High-Z Output Output High-Z Input Input High-Z Input High-Z Input High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z VALUE − ...

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... V ± 0 − 0 CE2 = V − 0 − CE2 = V − 0 TEST CONDITION = GND GND V OUT TC55VCM216ASTN40,55 MIN TYP   −0.5   2     MIN t cycle   1 µs   MIN ...

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... Data Hold Time DH Note and t are specified in time when an output becomes high impedance, and are not judged depending on OD ODO BD ODW an output voltage level. PARAMETER PARAMETER TC55VCM216ASTN40,55 TC55VCM216ASTN UNIT 40 55 MIN MAX MIN MAX      ...

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... Data Hold Time DH Note and t are specified in time when an output becomes high impedance, and are not judged depending on OD ODO BD ODW an output voltage level. PARAMETER PARAMETER TC55VCM216ASTN40,55 TC55VCM216ASTN UNIT 40 55 MIN MAX MIN MAX      ...

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... Input pulse level Timing measurements Reference level Output load Fig.1 : Input rise and fall time V Typ DD 90% 10% GND 1 V/ TC55VCM216ASTN40,55 TEST CONDITION 0 ns(Fig. TTL Gate(Fig.2) Fig.2 : Output load 90% Dout 10 × × 0 × 0.5 ...

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... ACC t CO1 t CO2 OEE t COE (See Note ODW (See Note 2) (See Note 5) TC55VCM216ASTN40, ODO t BD VALID DATA OUT OEW Hi-Z (See Note VALID DATA IN (See Note 5) 2002-07-04 8/14 Hi-Z ...

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... CE2 OUT Hi-Z I/O1~ (See Note 5) I/O1~16 WRITE CYCLE 3 (CE2 CONTROLLED) Address A0~A17 CE2 OUT Hi-Z I/O1~ (See Note 5) I/O1~16 TC55VCM216ASTN40,55 (See Note ODW t COE VALID DATA IN (See Note ...

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... HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. (See Note 4) CONTROLLED ODW Hi-Z t COE (See Note 5) TC55VCM216ASTN40, Hi VALID DATA IN 2002-07-04 10/14 ...

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... Note 1) DATA RETENTION MODE (See Note 2) t CDR − 0 (See Note 3) DATA RETENTION MODE t CDR 0.2 V (See Note 4) DATA RETENTION MODE (See Note 5) t CDR − 0 TC55VCM216ASTN40,55 ) MIN TYP MAX  1.5 3.6   10   2   5   0  ...

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... V or CE1 ≥ V − 0.2 V, CE2 ≤ 0 CE2 ≥ (5) When UB ( operating at the V the transition of V from 2.3(2.7) to 2.2V(2.4 V). DD TC55VCM216ASTN40,55 (min.) level, the operating current is given − 0 (min.) level, the operating current is given during the DDS1 ...

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... PACKAGE DIMENSIONS TSOPⅠ48-P-1214-0. Weight:0.35 g (typ 12.4 0.1 14.0 0.2 TC55VCM216ASTN40,55 Unit:mm 1.0 0.1 0.1 0.05 1.2max 0.5 0.1 2002-07-04 13/14 ...

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... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. TC55VCM216ASTN40,55 000707EBA 2002-07-04 14/14 ...