hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 18
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hyb18m1g16
Manufacturer Part Number
hyb18m1g16
Description
Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
Manufacturer
Qimonda
Datasheet
1.HYB18M1G16.pdf
(65 pages)
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1) All AC timing characteristics assume an input slew rate of 1.0 V/ns.
2) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes.
3) The transition time for address and command inputs is measured between
4) For command / address input slew rate ≥ 1V/ns.
5) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.
6) For command / address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
7) This parameter guarantees device timing. It is verified by device characterization but are not subject to production test.
Rev.1.0, 2007-03
10242006-Y557-TZXW
Parameter
Clock high-level width
Clock low-level width
Clock cycle time
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Input
CK
CK
CL = 3
CL = 2
fast slew rate
slow slew rate
fast slew rate
slow slew rate
Valid
t
CK
Symbol
t
t
t
t
t
t
18
t
CH
CL
CK
IS
IH
IPW
IS
Valid
t
IH
t
Address / Command Inputs Timing Parameters
CH
V
IH
0.45
0.45
6
12
1.1
1.3
1.1
1.3
2.7
and
min.
t
CL
V
IL
Valid
= Don't Care
- 6
.
0.55
0.55
–
–
–
–
–
–
–
max.
0.45
0.45
7.5
15
1.3
1.5
1.3
1.5
3.0
min.
Inputs Timing Parameters
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
- 7.5
0.55
0.55
–
–
–
–
–
–
–
max.
FIGURE 6
TABLE 8
Unit
t
t
ns
ns
ns
ns
CK
CK
Data Sheet
Note
1)
1)
1)2)
1)3)4)5)
1)3)6)
1)3)4)
1)3)6)
1)7)
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