hyb18m1g16 Qimonda, hyb18m1g16 Datasheet - Page 49

• Manufacturer Part Number: hyb18m1g16
• Description: Drams For Mobile Applications 1-gbit X16 Ddr Mobile-ram Rohs Compliant
• Manufacturer: Qimonda

1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to
3) Current state definitions:
4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable
5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle and no bursts are in progress.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
9) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
10) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to
11) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
12) Requires appropriate DM masking.
Rev.1.0, 2007-03
10242006-Y557-TZXW
Current State
Write (Auto-
Precharge
Disabled)
power-down or self refresh).
be issued to that bank when in that state. Exceptions are covered in the notes below.
Idle:
The bank has been precharged, and
Row Active:
A row in the bank has been activated, and
Read:
A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank
are determined by its current state and according to
Precharging:
Starts with registration of a PRECHARGE command and ends when
Row Activating:
Starts with registration of an ACTIVE command and ends when
Read with AP
Enabled:
Starts with registration of a READ command with Auto Precharge enabled and ends when
in the idle state.
Write with AP
Enabled:
Starts with registration of a WRITE command with Auto Precharge enabled and ends when
met. Once
positive clock edge during these states.
Refreshing:
Starts with registration of an AUTO REFRESH command and ends when
banks idle” state.
Accessing Mode
Register:
Starts with registration of a MODE REGISTER SET command and ends when
is in the “all banks idle” state.
Precharging All:
Starts with registration of a PRECHARGE ALL command and ends when
Auto Precharge disabled.
end the Read burst prior to issuing a WRITE command.
t
RP
is met, the bank is in the idle state.
L
L
L
CS
H
H
L
RAS CAS
L
L
H
t
RP
has been met.
H
L
L
WE
t
RCD
has been met. No data bursts / accesses and no register accesses are in progress.
Command / Action
READ (truncate Write and start Read burst)
WRITE (truncate Write and start Write burst)
PRECHARGE (truncate Write burst, start Precharge)
Table 19
.
t
RCD
49
Table 17
is met. Once
t
RP
is met. Once
t
t
RC
RP
) and after
is met. Once
is met. Once
t
MRD
t
has been met. Once
RCD
t
RP
is met, the bank is in the “row active” state.
t
XP
is met, the bank is in the “idle” state.
t
t
t
or
RP
RC
RP
t
RP
t
has been met. Once
XSR
is met, all banks are in the idle state.
is met, the DDR Mobile-RAM is in the “all
has been
has been met (if the previous state was
t
MRD
HY[B/E]18M1G16[0/1]BF
1-Gbit DDR Mobile-RAM
is met, the DDR Mobile-RAM
t
RP
is met, the bank is
Note
1)2)3)4)5)6)8)12)
1)2)3)4)5)6)8)
1)2)3)4)5)6)9)12)
Data Sheet