W83791SD Information Storage Devices, Inc, W83791SD Datasheet - Page 6

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W83791SD

Manufacturer Part Number
W83791SD
Description
Programmable Speech Synthesizer With 133 Int/ext Event Triggers
Manufacturer
Information Storage Devices, Inc
Datasheet

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5. PIN DESCRIPTION
I/O
I/O
I/OD
OUT
IN
IN
AIN
EVNTRP5
EOP
REXT
ADDR
CLKOUT
DATA
CTRL
MODE
SPEAKER
A0
A1
VDD (5V)
GND
SLOTOCC#
NC
SCL
SDA
+3.3VIN
EVNTRP1-4
PIN NAME
t
ts
12t
12ts
8ts
12
- TTL level bi-directional pin with 12 mA source-sink capability
- TTL level and schmitt trigger with 12 mA source-sink capability
- TTL level and schmitt trigger open drain output with 8 mA sink capability
- Output pin with 12 mA source-sink capability
- TTL level input pin
- TTL level input pin and schmitt trigger
- Input pin (Analog)
12, 13, 17, 18,
19, 20, 24, 25,
14, 16, 27, 28,
31, 32, 33, 35,
23, 26, 37, 42,
36, 38, 39, 40
29, 30, 41
PIN NO.
43, 44
45-48
10
11
15
21
22
34
2
3
4
5
7
8
9
1
6
POWE
GROU
I/OD
OUT
OUT
OUT
OUT
OUT
TYPE
I/O
I/O
AIN
IN
IN
ND
IN
IN
IN
IN
IN
R
12ts
12t
ts
ts
ts
ts
t
t
t
8ts
12
12
12
12
12
Event trapping to selection speech output sound.
End of Process signal input from cascaded Flash.
Resistor (Rosc) connects to VSB to adjust ring oscillator
frequency.
Speech address pulse output, connect to W55FXX. When this
pin translates from logic high to logic low, it will latch the data pin
6 and shift it into a speech flash address counter.
Speech clock output, for speech data read-out and write-in,
connect to W55FXX. When this pin translates from logic high to
logic low, the data pin 6 will be latched by this clock.
Serial data input/output, connect to W55FXX. The pin is latched
by CLKOUT and ADDR acted as speech data and address
respectively.
Output clock numbers of this pin decide which mode is selected.
Connect to W55FXX.
Output mode signal to W55FXX serial Flash.
Current type output driving an external speaker. The function is
only working in VSB 5V OK.
I
I
+5V VDD pins.
Ground pins
CPU presence signal. 0 means CPU is present. 1 means CPU is
absent.
No connect.
Serial Bus Clock.
Serial Bus bi-directional Data.
0V to 4.096V FSR Analog Inputs.
Event trapping to selection speech output sound.
2
2
C device address bit0 trapping during 5VDD power on.
C device address bit1 trapping during 5VDD power on.
- 3 -
Publication Release Date: January 18, 2005
W83791SD/W83791SG
DESCRIPTION
Revision 1.1

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