tc9446fg TOSHIBA Semiconductor CORPORATION, tc9446fg Datasheet
tc9446fg
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tc9446fg Summary of contents
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... TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio TC9446FG is the various digital signal processor for decoding. It contains the decode processing program which embraced encoding signals, such as Dolby Digital (AC-3)/Pro Logic (Note 1), MPEG2 audio and DTS (Note 2). ...
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... V 95 SSDL SCKI SSX 100 DDX 1 2 TC9446FG TC9446FG LOCK 47 CKO 46 V SSA 45 CKI 44 AMPO 43 AMPI 42 PLON 41 V DDA 40 PDO 39 TSTSUB2 ...
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... Y0, Y2 MAC Round/Limiter 3 Timing Address operator × 2 DLL X pointer Y pointer C pointer register register register Bus switch 3 External SRAM 17 interface General output 8 port ALU 4 Flag A3 DIT Round/Limiter TC9446FG SCKO SCKI DLON LPFO ADn IOn POn FIn TXO 2005-09-28 ...
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... Test input-3 (L: test, H: normal operation SPDIF input ⎯ Digital ground SS Description of Pin Functions 2 C bus) 4 TC9446FG Remarks Pull-up resistor, Schmitt input Pull-down resistor, Schmitt input Schmitt input Schmitt input Schmitt input/ Open-drain output Schmitt input Pull-up resistor, Schmitt input Pull-up resistor, ...
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... Address output-11 for external SRAM 76 AD12 O Address output-12 for external SRAM 77 AD13 O Address output-13 for external SRAM Description of Pin Functions 5 TC9446FG Remarks Pull-up resistor, Schmitt input Tri-state output Pull-up resistor, Schmitt input Pull-up resistor, Schmitt input Tri-state output Pull-up resistor, Schmitt input ...
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... XI clock rd “L” 3 times of XI clock th “H” 6 times of XI clock 6 TC9446FG Remarks Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor Pull-up resistor ...
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... Description of Operation 1. Micro Controller Interface The TC9446FG can perform transmission and reception of serial data with a micro controller in the 2 serial mode or the I C mode. MIMD terminal performs a change in the serial mode and the I are performed at MSB first. The use terminal and the function in the serial mode and the I The bit composition bit command is shown in Table 2 ...
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... As for TC9446FG, RAM is assigned 128 words of program address 0000h-007Fh, and the interruption vector address is become 0000h-0009h. Therefore, in order to operate TC9446FG, it needs to interrupt and a program needs to be booted to a vector address. In addition, a program load needs to be continuously performed to an interruption vector address to store a program in 000Ah-007Fh. ...
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... Program starting Figure 2 Procedure of Program Boot and Program Start Setting “H” for bit of program boot and soft reset bit. Program data is 20 bit lower assign possible to do the program boot for address of 007Fh maximum. It finished the program boot. 9 TC9446FG 2005-09-28 ...
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... Write of 24 bit data The number of words of data written in while data required for the 16 bit address bit command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446FG during program operation is set up. And, 24 bit data of the number required after transmitting a 24 bit command of words is written in. ...
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... Read-out of 24 bit data The number of words of data read while data required for the 16 bit address bit command is set up and R/W bit is set to “H”, when reading data of TC9446FG from a MCU during program operation is set up. And, after transmitting a 24 bit command, MIACK = “L” is checked and 24 bit data of the required number of words is read. MIACK = “ ...
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... Transmission of 24 bit command (soft reset ON/OFF = 0000x0h) MICS = “H” Soft reset ON/OFF Figure 5 Procedure of ON/OFF of Soft Reset It is possible to transmit the command data of soft reset ON at MIACK = “H”. Soft reset ON: Bit = “1”. Soft reset OFF: Bit = “0”. 12 TC9446FG 2005-09-28 ...
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... MICS terminal = “H”. Moreover, although it checks that MIACK terminal is “L” after setting MICS terminal to “L” in case a MCU starts access to TC9446FG, MCU can judge that an internal program is a incorrect operation state, when the state of MIACK = “H” continues. ...
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... However, at the time of “H”, ACK bit performs Start Condition again, without performing STOP Condition, and transmits I bit command after Address transmission. And, at the time of data Write of TC9446FG, Write of 24 bit data of the number (1-16 word) of words set bit command is performed from a MCU, and, finally, END Condition is transmitted. ...
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... The interval more is required until next START. (3Bh) 24 bit Read DATA (1 word to 16 word Add ( (M) A RD(L) These of ACK are retarned to TC9446FG from MCU This ACK is MCU A COMMAND (L) A STOP TC9446FG A STOP A STOP set up at “H”. ...
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... As for TC9446FG, RAM is assigned 128 words of program address 0000h-007Fh, and the interruption vector address is become 0000h-0009h. Therefore, in order to operate TC9446FG, it needs to interrupt at least and a program needs to be booted to a vector address. In addition, a program load needs to be continuously performed to an interruption vector address to store a program in 000Ah-007Fh ...
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... At the time of ACK = “H”, it resumes from START Condition. The bit of program boot and soft reset is set to “H”. Program data is 20 bits of low-rank stuffing. Boot is possible to the address of a maximum of 007Fh. The completion of program boot. At the time of ACK = “H”, it resumes from START Condition. 17 TC9446FG 2005-09-28 ...
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... Write of 24 bit data The number of words of data written in while data required for the 16 bit address bit command is set up and R/W bit is set to “L”, when writing in data from a MCU to TC9446FG during program operation is set up. And, 24 bit data of the number required after transmitting a 24 bit command of words is written in. ...
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... Read of 24 bit data The number of words of data read while data required for the 16 bit address bit command is set up and R/W bit is set to “L”, when reading data of TC9446FG from a MCU during program operation is set up. And, after transmitting a 24 bit command, I about 6 ms, and it transmits with START Condition ...
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... ACK bit is “H” continued. A MCU can perform incorrect operation detection by seeing this ACK bit. That is, since TC9446FG are in a incorrect operation state when it is “H” fixation, even if ACK bit passes about more, ACK bit is disregarded, soft reset is turned ON, and each setup of TC9446FG is performed again. At the time of ACK = “ ...
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... Setting Procedure Until it Starts Decode Program Operation Setting procedure until it starts operation of the decode program built in TC9446FG is shown below. First, 10 words program data is transmitted in the program boot mode after release of the power-on reset at the time of a power-supply injection. However, when there is a program required for others, program data of a maximum of 128 words can be transmitted ...
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... Clock output CKO V DDA 46 V SSA V External clock input SSA 45 (when CKI does not use, it CKI connect AMPO AMPI L: CKI/XI clock DD H: VCO clock 42 PLON 41 V DDA 40 PDO 37 FCONT V SSA 34 DIR input RX 31 DIT output TXO 22 TC9446FG line 2005-09-28 ...
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... Figure 18 Internal Operation Timing at Time of Error Table 3 Release Time After the Lock Detection Operation Sampling Frequency (kHz) Data of Receiving Demodulation V-3 V level shifter (ms) A 384.0 278.6 256.0 128.0 23 TC9446FG DIR (3 V input) Channel Status t (ms) B 288.0 209.0 192.0 96.0 2005-09-28 ...
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... Objective frequency Lower than objective frequency Hiz SSX External clock input 96 (when the SCKI does not use, SCKI it connect to V line Clock output SCKO 93 DLCKS 92 DLON LPFO TC9446FG 2005-09-28 ...
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... MIPS operation) 73.728 MHz (36 MIPS operation) 98.304 MHz (49 MIPS operation) 100.00 MHz (50 MIPS operation) 108.00 MHz (54 MIPS operation) to 120 MHz (60 MIPS operation) Not available 25 TC9446FG DLL Oscillation Clock SCKI input (DLL = off input * 4 times rd XI input * 3 times th XI input * 6 times rd ...
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... Data input/output terminal for external SRAM (8 bit I/O) IO0 to IO7 terminal times accessing at 24 bit I/O. Address output terminal for external SRAM AD0 to AD16 terminal It can access to address 00000h to 20000h. Example of High-speed 1 M SRAM connection TC9446FG (3 SRAM (3 AD0¯AD16 AD0¯AD16 8 IO0¯IO7 IO0¯IO7 CE ...
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... DATA IN2 LRCKI BCKI SCKI Figure 22 Example of AD/DA Converter Connection TC9446FG SDI0 (fs fs/fs) SDO0 (not used) TXO (2 fs/fs) DIT SDO1 SDO2 SDO3 LRCKOA (2 fs/fs) BCKOA LRCKA BCKA LRCKOB (not used) BCKOB (not used) LRCKB BCKB SDI1 (not used) CKO 27 TC9446FG DIR input DIT output 2005-09-28 ...
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... Dolby Digital IEC958 (AC- decode Note 9: “Dolby”,”Pro Logic”, and the double-D symbol are trademarks of Dolby Laboratories. Configuration SFC C/Sch delay 2 ch Down Mix 3D sound Dolby SFC Pro Logic Dolby 3D sound Pro Logic 3D sound 28 TC9446FG 2005-09-28 ...
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... R IN MCU TC9446FG MCU Interface 384 fs DIR (VCO) TIMING 384 fs DLL ( × 6) 110.592 MHz SDO0¯3 DECODE (55 MIPS) 29 CKO 384 fs LRCKOA fs BCKOA 64 fs DAC LRCKA BCKA DAC DAC DIT TXO (IEC958) TC9446FG L OUT R OUT SL OUT SR OUT C OUT LFE OUT 2005-09-28 ...
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... Please determine constant value according to the characteristic of a circuit in the case of use of this product. In addition, the constant value in the example of an application circuit is for explaining operation of this product, and application, and does not offer a guarantee of operation. TC9446FG (top view) AUDIO I/F (3.3 V) and V line TC9446FG SRAM I/F (3 AUDIO SCK V SS MCU I/F LOCK ...
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... DD = 150 MHz 75 MIPS f ⎯ opr I DD operating ⎯ V IH1 XI pin, (Note 14) ⎯ V IL1 ⎯ OH1 OH XO pin ⎯ OL1 OL 31 TC9446FG = 3.3 V) Min Typ. Max Unit 3.0 3.3 3.6 V 3.1 3.3 3 ⎯ ⎯ 120 MHz th ⎯ ⎯ 150 MHz ⎯ 110 160 mA ⎯ ⎯ ...
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... MIDIO pin = ⎯ I OL6 = (Note 12), ⎯ Rup V (Note 15), IN (Note 16) ⎯ (Note 13 TC9446FG Min Typ. Max Unit ⎯ ⎯ 2.8 V ⎯ ⎯ 0.5 ⎯ ⎯ ± 10 µ A ⎯ ⎯ ± 10 ⎯ ⎯ − ⎯ ⎯ 15 ⎯ ...
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... C BCL L ⎯ pF kHz t C DO1 L ⎯ pF kHz t C DO2 L ⎯ pF kHz C DCLR L 33 TC9446FG Min Typ. Max Unit ⎯ ⎯ 30 MHz ⎯ ⎯ 37 MHz ⎯ ⎯ ⎯ ⎯ ⎯ ...
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... MIDIO input data setup time MIDIO input data hold time MIDIO output data delay time MICS “H” duration MIACK output delay time MILP rise-MICS rise setup time Note 18: “H” duration of MIACK signal depends on firmware of TC9446FG Mode ( MICK , MIDIO) MICK clock frequency f MICK “ ...
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... MIPS operating ⎯ pF, 75 MIPS operating ⎯ pF, 75 MIPS operating t C OES L ⎯ pF, 75 MIPS operating t C OEH L 35 TC9446FG Min Typ. Max Unit ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 27 ⎯ ...
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... CKO 50% 100% LRCKOx 0% LRCKx/ LRCKOx t LBH BCKx/ BCKOx SDIx SDOx CIH SIH L CIL SIL × 100 (%) /( 90% t RRS t DCLR 50% t BCK t t BCL BCH t LBS t t SDI HDI t t DO1 DO2 36 TC9446FG t WRS 2005-09-28 ...
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... MICS ΜΙΑCΚ MICK MILP MIDIO MIDIO MICS ΜΙΑCΚ MICK MILP MIDIO MIDIO DATA IN DATA OUT DATA IN DATA OUT 37 TC9446FG 2005-09-28 ...
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... I C mode ( MICK , MIDIO) RST MIDIO t STB (SDA) t BUF MIDIO (SDA) MICK (SCL SCH SCS 38 TC9446FG ECS 2005-09-28 ...
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... READ cycle timing AD0-AD16 ADDRESS t ASR t AHR IO0-IO7 (5-2) WRITE cycle timing AD0-AD16 ADDRESS t t ASW AHW OES IO0-IO7 DATA OUT PCR t ACC DATA PCW TC9446FG t COD t OEH 2005-09-28 ...
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... Package Dimensions P-QFP100-1420-0.65Q Weight: 1.57 g (typ.) (Note) Palladium plate 40 TC9446FG Unit : mm 2005-09-28 ...
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... TC9446FG 2005-09-28 ...