attiny25v ATMEL Corporation, attiny25v Datasheet - Page 53

• Manufacturer Part Number: attiny25v
• Description: Microcontroller With 2/4/8k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

9.3.2
9.3.3
2586K–AVR–01/08
GIMSK – General Interrupt Mask Register
GIFR – General Interrupt Flag Register
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT5:0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt
Vector. PCINT5:0 pins are enabled individually by the PCMSK0 Register.
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
Bit
0x3B
Read/Write
Initial Value
Bit
0x3A
Read/Write
Initial Value
ISC01
0
0
1
1
Interrupt 0 Sense Control
7
–
R
0
7
–
R
0
ISC00
0
1
0
1
6
INT0
R/W
0
6
INTF0
R/W
0
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
5
PCIE
R/W
0
5
PCIF
R/W
0
4
–
R
0
4
–
R
0
3
–
R
0
3
–
R
0
2
–
R
0
2
–
R
0
ATtiny25/45/85
1
–
R
0
1
–
R
0
0
–
R
0
0
–
R
0
GIMSK
GIFR
53