attiny25v ATMEL Corporation, attiny25v Datasheet - Page 74

• Manufacturer Part Number: attiny25v
• Description: Microcontroller With 2/4/8k Bytes In-system Programmable Flash
• Manufacturer: ATMEL Corporation

11.7
11.7.1
11.7.2
74
Modes of Operation
ATtiny25/45/85
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output
mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-
put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare
Match
For detailed timing information refer to
13
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the Compare Match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
Figure 11-7. CTC Mode, Timing Diagram
TCNTn
OCn
(Toggle)
Period
in
“Timer/Counter Timing Diagrams” on page
(See “Compare Match Output Unit” on page
1
2
Figure
3
11-10,
78.
72.).
Figure
Figure
4
11-11,
11-7. The counter value (TCNT0)
Figure 11-12
OCnx Interrupt Flag Set
(COMnx1:0 = 1)
and
2586K–AVR–01/08
Figure 11-