attiny25v ATMEL Corporation, attiny25v Datasheet - Page 95
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attiny25v
Manufacturer Part Number
attiny25v
Description
Microcontroller With 2/4/8k Bytes In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY25V.pdf
(231 pages)
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12.3.5
12.3.6
12.3.7
2586K–AVR–01/08
OCR1B – Timer/Counter1 Output Compare RegisterB
OCR1C – Timer/Counter1 Output Compare RegisterC
TIMSK – Timer/Counter Interrupt Mask Register
The output compare register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.
This register has the same function in normal mode and PWM mode.
• Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector
$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register.
• Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector
$009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one)
in the Timer/Counter Interrupt Flag Register.
Bit
0x2B
Read/Write
Initial value
Bit
0x2D
Read/Write
Initial value
Bit
0x39
Read/Write
Initial value
MSB
MSB
R/W
R/W
R
7
0
7
0
7
1
-
OCIE1A
R/W
R/W
R/W
6
0
6
1
6
0
OCIE1B
R/W
R/W
5
0
5
1
R/W
5
0
R/W
R/W
OCIE0A
4
0
4
1
R/W
4
0
R/W
R/W
3
0
3
1
OCIE0B
R/W
3
0
R/W
R/W
2
0
2
1
TOIE1
R/W
2
0
ATtiny25/45/85
R/W
R/W
1
0
1
1
TOIE0
R/W
1
0
LSB
R/W
LSB
R/W
0
0
0
1
R
0
0
-
OCR1B
OCR1C
TIMSK
95
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