p89lpc930fdh NXP Semiconductors, p89lpc930fdh Datasheet - Page 32

• Manufacturer Part Number: p89lpc930fdh
• Description: 8-bit Microcontrollers With Two-clock 80c51 Core 4 Kb/8 Kb 3 V Flash With 256-byte Data Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14472
Product data
Fig 9. SPI block diagram.
SPI STATUS REGISTER
BY 4, 16, 64, 128
CPU clock
DIVIDER
SELECT
SPI CONTROL
The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:
Typical connections are shown in Figures 10, 11, and 12.
•
•
interrupt
request
SPI clock (master)
SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and
flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal
is output in the master mode and is input in the slave mode. If the SPI system is
disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port
functions.
SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave
device uses its SS pin to determine whether it is selected.
SPI
MSTR
SPEN
Rev. 05 — 15 December 2004
internal
data
bus
SPI CONTROL REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
CLOCK LOGIC
8-bit microcontrollers with two-clock 80C51 core
clock
P89LPC930/931
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
M
M
M
S
S
S
002aaa434
SPICLK
MISO
MOSI
P2.3
P2.2
P2.5
P2.4
SS
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