p89lpc972fn NXP Semiconductors, p89lpc972fn Datasheet - Page 41

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p89lpc972fn

Manufacturer Part Number
p89lpc972fn
Description
8-bit Microcontroller With Accelerated Two-clock 80c51 Core 2kb/4 Kb/8 Kb Wide-voltage Byte-erasable ?ash
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
P89LPC97X_1
Preliminary data sheet
Fig 15. Watchdog timer in Watchdog mode (WDTE = 1)
oscillator
oscillator
400 kHz
25 kHz
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
(CLKCON.5)
sequence.
WDMOD
0
1
7.28.1 Software reset
7.28.2 Dual data pointers
7.29.1 General description
7.28 Additional features
7.29 Flash program memory
watchdog
oscillator
PCLK
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
The P89LPC970/971/972 flash memory provides in-circuit electrical erasure and
programming. The flash can be erased, read, and written as bytes. The Sector and Page
Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase
operation will erase the entire program memory. ICP using standard commercial
programmers is available. In addition, IAP and byte-erase allows code memory to be used
for non-volatile data storage. On-chip erase and write timing generation contribute to a
user-friendly programming interface. The P89LPC970/971/972 flash reliably stores
memory contents even after 100,000 erase and program cycles. The cell is designed to
0
1
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
oscillator
crystal
(CLKCON.4)
XTALWD
0
1
WDCON (A7H)
32
Rev. 01 — 17 December 2009
8-bit microcontroller with accelerated two-clock 80C51 core
PRE2
PRESCALER
PRE1
PRE0
SHADOW REGISTER
P89LPC970/971/972
-
-
8-BIT DOWN
WDL (C1H)
COUNTER
WDRUN
WDTOF
© NXP B.V. 2009. All rights reserved.
WDCLK
reset
002aae542
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