p89lpc9401 NXP Semiconductors, p89lpc9401 Datasheet - Page 38

• Manufacturer Part Number: p89lpc9401
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable Flash With 32 Segment X 4 Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
P89LPC9401_1
Preliminary data sheet
7.26.10 Data pointer
7.26.4.1 Internal clock
7.26.4 Oscillator
7.26.5 Timing
7.26.6 Display register
7.26.7 Segment outputs
7.26.8 Backplane outputs
7.26.9 Display RAM
An internal oscillator provides the clock signals for the internal logic of the LCD controller
and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the
clock starts.
The LCD controller timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
the internal or an external clock.
Frame frequency = f
A display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs, and each column of the display RAM.
The LCD drive section includes 32 segment outputs S0 to S31. The segment output
signals are generated according to the multiplexed backplane signals and the display
latch data. When less than 32 segment outputs are required, the unused segment outputs
should be left open-circuit.
The LCD drive section has four backplane outputs BP0 to BP3. The backplane output
signals are generated in based on the selected LCD drive mode. If less than four
backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3
multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent
outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive
mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be
paired to increase the drive capabilities. In the static drive mode the same signal is carried
by all four backplane outputs and they can be connected in parallel for very high drive
requirements.
The display RAM is a static 32
correspondence between the RAM addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs. The first RAM column
corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications
the segment data of the second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
The Display RAM is addressed using the data pointer. Either a single byte or a series of
display bytes may be loaded into any location of the display RAM.
8-bit two-clock 80C51 microcontroller with 32 segment
osc(LCD)
Rev. 01 — 5 September 2005
/ 24.
4-bit RAM which stores LCD data. There is a one-to-one
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
P89LPC9401
4 LCD driver
38 of 59