p87c591vfb NXP Semiconductors, p87c591vfb Datasheet - Page 97

• Manufacturer Part Number: p87c591vfb
• Description: Single-chip 8-bit Microcontroller With Can Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
15.2.14.4 Slave Transmitter Mode
In the slave transmitter mode, a number of data bytes are
transmitted to a master receiver (see Figure 40). Data
transfer is initialized as in the slave receiver mode. When
S1ADR and S1CON have been initialized, SIO1 waits until
it is addressed by its own slave address followed by the
data direction bit which must be “1” (R) for SIO1 to operate
in the slave transmitter mode. After its own slave address
and the R bit have been received, the serial interrupt flag
(SI) is set and a valid status code can be read from S1STA.
This status code is used to vector to an interrupt service
routine, and the appropriate action to be taken for each of
these status codes is detailed in Table 64. The slave
transmitter mode may also be entered if arbitration is lost
while SIO1 is in the master mode (see state B0H).
If the AA bit is reset during a transfer, SIO1 will transmit the
last byte of the transfer and enter state C0H or C8H. SIO1
is switched to the not addressed slave mode and will
ignore the master receiver if it continues the transfer. Thus
the master receiver receives all 1s as serial data. While AA
is reset, SIO1 does not respond to its own slave address
or a general call address. However, the I
monitored, and address recognition may be resumed at
any time by setting AA. This means that the AA bit may be
used to temporarily isolate SIO1 from the I
15.2.14.5 Miscellaneous States
There are two S1STA codes that do not correspond to a
defined SIO1 hardware state (see Table 65). These are
discussed below.
2000 Jul 26
S1STA = F8H:
This status code indicates that no relevant information is
available because the serial interrupt flag, SI, is not yet
set. This occurs between other states and when SIO1 is
not involved in a serial transfer.
S1STA = 00H:
This status code indicates that a bus error has occurred
during an SIO1 serial transfer. A bus error is caused
when a START or STOP condition occurs at an illegal
position in the format frame. Examples of such illegal
positions are during the serial transfer of an address
byte, a data byte, or an acknowledge bit. A bus error
may also be caused when external interference disturbs
the internal SIO1 signals. When a bus error occurs, SI is
set. To recover from a bus error, the STO flag must be
set and SI must be cleared. This causes SIO1 to enter
the not addressed slave mode (a defined state) and to
clear the STO flag (no other bits in S1CON are affected).
The SDA and SCL lines are released (a STOP condition
is not transmitted).
Single-chip 8-bit microcontroller with CAN controller
2
C bus is still
2
C bus.
97
15.2.15 S
The SIO1 hardware has facilities to handle the following
special cases that may occur during a serial transfer:
Simultaneous Repeated START Conditions from Two
Masters.
A repeated START condition may be generated in the
master transmitter or master receiver modes. A special
case occurs if another master simultaneously generates a
repeated START condition (see Figure 41). Until this
occurs, arbitration is not lost by either master since they
were both transmitting the same data. If the SIO1
hardware detects a repeated START condition on the I
bus before generating a repeated START condition itself,
it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a
STOP condition, SIO1 will transmit a normal START
condition (state 08H), and a retry of the total serial data
transfer can commence.
15.2.15.1 Data Transfer after loss of Arbitration
Arbitration may be lost in the master transmitter and
master receiver modes (see Figure 33). Loss of arbitration
is indicated by the following states in S1STA; 38H, 68H,
78H, and B0H (see Figures 37 and 38).
If the STA flag in S1CON is set by the routines which
service these states, then, if the bus is free again, a
START condition (state 08H) is transmitted without
intervention by the CPU, and a retry of the total serial
transfer can commence.
15.2.15.2 Forced Access to the I
In some applications, it may be possible for an
uncontrolled source to cause a bus hang-up. In such
situations, the problem may be caused by interference,
temporary interruption of the bus or a temporary
short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START
or masks a STOP condition, then the I
indefinitely. If the STA flag is set and bus access is not
obtained within a reasonable amount of time, then a forced
access to the I
setting the STO flag while the STA flag is still set. No
STOP condition is transmitted. The SIO1 hardware
behaves as if a STOP condition was received and is able
to transmit a START condition. The STO flag is cleared by
hardware (see Figure 42).
OME
2
S
C bus is possible. This is achieved by
PECIAL
C
ASES
Preliminary Specification
2
C bus
2
C bus stays busy
P8xC591
2
C