km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 28

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
The second bubble type t
command) by the controller between a WR and RD
command on the COL pins when there is a WR-WR-RD
sequence to the same device. This bubble enables write data
to be retired from the write buffer without being lost, and is
COL4
CTM/CFM
DQA8..0
DQB8..0
ROW2
COL4
CTM/CFM
DQA8..0
ROW2
DQB8..0
..COL0
..ROW0
..COL0
..ROW0
t
DBUB1
D (y2)
T
0
T
0
T
1
T
t
1
RD z1
T
CBUB2
RD z1
Q (x2)
2
T
ACT a0
2
T
ACT a0
3
T
3
Transaction b: WR
Transaction y: WR
Transaction c: WR
T
Transaction a: RD
Transaction d: RD
Transaction f: WR
Transaction z: RD
Transaction e: RD
Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length
Figure 21: Interleaved Read Transaction with Two Dualoct Data Length
4
T
Transaction y: RD
Transaction a: RD
Transaction b: RD
Transaction d: RD
Transaction z: RD
Transaction c: RD
Transaction e: RD
Transaction f: RD
CBUB2
4
T
5
T
5
PREX y3
RD z2
T
RD z2
Q (y1)
6
T
6
T
t
7
T
DBUB2
is inserted (as a NOCOP
7
T
8
T
t
8
T
RCD
9
T
RD a1
9
T
RD a1
Q (y2)
10
T
10
T
ACT b0
11
T
11
T
12
T
ACT b0
b0 = {Da,Ba+2,Rb}
d0 = {Da,Ba+6,Rd}
y0 = {Da,Ba+4,Ry}
12
z0 = {Da,Ba+6,Rz}
c0 = {Da,Ba+4,Rc}
T
f0 = {Da,Ba+2,Rf}
t
b0 = {Da,Ba+2,Rb}
d0 = {Da,Ba+6,Rd}
y0 = {Da,Ba+4,Ry}
13
a0 = {Da,Ba,Ra}
e0 = {Da,Ba,Re}
z0 = {Da,Ba+6,Rz}
c0 = {Da,Ba+4,Rc}
RBUB1
PREX z3
T
f0 = {Da,Ba+2,Rf}
13
a0 = {Da,Ba,Ra}
PREX z3
e0 = {Da,Ba,Re}
RD a2
Q (z1)
T
14
RD a2
Q (z1)
T
14
T
15
T
15
T
t
T
16
CAC
16
T
17
T
17
Q (z2)
T
RD b1
18
Q (z2)
T
18
T
ACT c0
MSK (y2)
19
T
WR b1
t
19
Page 25
T
CBUB1
20
T
ACT c0
20
T
21
T
b1 = {Da,Ba+2,Cb1}
d1 = {Da,Ba+6,Cd1}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
c1 = {Da,Ba+4,Cc1}
f1 = {Da,Ba+2,Cf1}
PREX a3
21
Q (a1)
T
b1 = {Da,Ba+2,Cb1}
d1 = {Da,Ba+6,Cd1}
a1 = {Da,Ba,Ca1}
t
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
c1 = {Da,Ba+4,Cc1}
e1 = {Da,Ba,Ce1}
f1 = {Da,Ba+2,Cf1}
RD b2
Q (a1)
22
RC
explained in detail in Figure 18. There would be no bubble if
address c0 and address d0 were directed to different devices.
This bubble appears on the DQA and DQB pins as t
between a write data dualoct D and read data dualoct Q. This
bubble also appears on the ROW pins as t
T
a1 = {Da,Ba,Ca1}
e1 = {Da,Ba,Ce1}
22
T
PREX a3
23
WRA b2
T
23
T
24
T
24
T
25
T
25
Q (a2)
T
RD c1
Q (a2)
26
T
26
T
ACT d0
MSK (b1)
27
T
WR c1
27
T
28
T
28
T
29
T
29
PREX b3
D (b1)
T
30
t
RD c2
Q (b1)
T
RBUB2
b2= {Da,Ba+2,Cb2}
d2= {Da,Ba+6,Cd2}
y2= {Da,Ba+4,Cy2}
30
z2= {Da,Ba+6,Cz2}
c2= {Da,Ba+4,Cc2}
f2= {Da,Ba+2,Cf2}
T
b2= {Da,Ba+2,Cb2}
d2= {Da,Ba+6,Cd2}
y2= {Da,Ba+4,Cy2}
a2= {Da,Ba,Ca2}
e2= {Da,Ba,Ce2}
z2= {Da,Ba+6,Cz2}
c2= {Da,Ba+4,Cc2}
31
MSK (b2)
f2= {Da,Ba+2,Cf2}
T
WRA c2
a2= {Da,Ba,Ca2}
e2= {Da,Ba,Ce2}
31
T
32
T
t
32
T
RR
33
T
33
D (b2)
T
RD d1
Q (b2)
34
T
34
T
ACT e0
35
MSK (c1)
T
NOCOP
Rev. 1.01 Oct. 1999
35
T
Direct RDRAM
T
36
ACT d0
36
T
t
37
T
CBUB2
37
PREX c3
D (c1)
T
same bank as transaction a
Transaction e can use the
Q (c1)
38
RDd2
T
same bank as transaction a
38
T
Transaction e can use the
MSK (c2)
39
T
NOCOP
39
T
40
b3 = {Da,Ba+2}
d3 = {Da,Ba+6}
T
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
c3 = {Da,Ba+4}
f3 = {Da,Ba+2}
40
b3 = {Da,Ba+2}
d3 = {Da,Ba+6}
a3 = {Da,Ba}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
c3 = {Da,Ba+4}
T
t
e3 = {Da,Ba}
f3 = {Da,Ba+2}
RBUB2
DBUB1
41
T
a3 = {Da,Ba}
e3 = {Da,Ba}
41
D (c2)
T
ACT f0
RD e1
Q (c2)
42
T
42
T
43
T
ACT e0
43
.
T
RDd0
44
T
44
T
45
T
DBUB2
45
PREX d3
T
Q (d1)
46
T
RD e2
46
T
47
T
47
RDf1
™