km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 39

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the t
t
TCLS1..0 - Specifies the t
t
TCDLY0 - Specifies the t
t
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values “011” (3 t
(5 t
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t
equal to the t
offset between a ROW packet (which places a device at
ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values “0111” (7 t
“1010” (10 t
which matches the largest t
4 t
system. Thus, if an RDRAM with t
9 t
programmed to 9 t
15 14 13 12 11 10 9
CYCLE
CYCLE
CYCLE
15 14 13 12 11 10 9
0
0
Control Register: TPARM
Control Register: TFRM
CYCLE
CYCLE
CYCLE
CYCLE
0
0
units. This should be “10” (2 t
units. Should be “10” (2 t
units. This adds a programmable delay to Q
0
0
) that is present in an RDRAM in the memory
were present, then TFRM would be
).
units. This value must be greater than or
0
0
CYCLE
Figure 40: TFRM Register
FRM,MIN
0
0
0
0
). TFRM is usually set to the value
CYCLE
0
0
parameter. This is the minimum
8
0
8
0
CYCLE
.
CDLY0-C
CLS-C
CAS-C
RCD,MIN
7
0
7
0
6
6
0
) through “101”
TCDLY0
core parameter in
core parameter in
CYCLE
CYCLE
core parameter in
5
5
0
RCD,MIN
parameter (modulo
Address: 049
CYCLE
4
4
0
Address: 048
).
) through
3
3
TCLS
TFRM3..0
Figure 39: TPARM Register
=
).
2
2
1
1
TCAS
16
0
0
16
Page 36
The equations relating the core parameters to the
datasheet parameters follow:
.
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t
parameter in t
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values “000” (0 t
“010” (2 t
TCDLY0
t
t
t
t
t
t
15 14 13 12 11 10 9
0
CAS-C
CLS-C
CPS-C
OFFP
RCD
CAC
Control Register: TCDLY1
011
011
011
100
101
0
= t
= 3 t
= t
(see table below for programming ranges)
= t
= 1 t
= 4 t
= 2 t
= 2 t
0
3•t
3•t
3•t
4•t
5•t
t
CDLY0-C
RCD-C
RCD-C
CPS-C
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
0
Figure 41: TRDLY Register
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
0
+ 1 t
+ t
TCDLY1
- 1 t
). Refer to Figure 39 for more details.
000
001
010
010
010
0
+ t
CAS-C
CYCLE
CYCLE
CLS-C
units. This adds a programmable
0
0 t
1 t
2 t
2 t
2 t
t
CDLY1-C
Not programmable
+ t
8
0
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
Rev. 1.01 Oct. 1999
Direct RDRAM
+ t
CLS-C
- t
7
0
CLS-C
CDLY0-C
6
0
- 1 t
5
0
10 t
11 t
12 t
8 t
9 t
CYCLE
t
Address: 04a
CAC
CYCLE
CYCLE
4
0
CDLY1-C
CYCLE
CYCLE
CYCLE
CYCLE
+ t
3
0
CDLY1-C
) through
2
TCDLY1
core
1
16
0
™