km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 51

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
RSL - Receive Timing
Figure 54 is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.
The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per t
CFMN
CFM
ROW
DQA
DQB
COL
V
X-
t
DR
Figure 54: RSL Timing - Data Signals for Receive
CYCLE
t
interval.
DF
Page 48
The set/hold window of the sample points is t
sample points are centered at the 0% and 50% points of a
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the V
The t
at the 20% and 80% points of the input transition.
t
S
even
DR
REF
and t
t
H
voltage point of the input transition.
DF
0.5•t
rise- and fall-time parameters are measured
V
V
CYCLE
CM
X+
Rev. 1.01 Oct. 1999
t
Direct RDRAM
S
odd
t
H
S
/t
H.
The
V
V
V
80%
50%
20%
V
80%
20%
V
REF
CIH
DIH
CIL
DIL
™