km416rd8ac Samsung Semiconductor, Inc., km416rd8ac Datasheet - Page 53

• Manufacturer Part Number: km416rd8ac
• Description: 128/144mbit Rdram 256k X 16/18 Bit X 2*16 Dependent Banks Direct Rdramtm
• Manufacturer: Samsung Semiconductor, Inc.

KM416RD8AC(D)/KM418RD8AC(D)
CMOS - Receive Timing
Figure 56 is a timing diagram which shows the detailed
requirements for the CMOS input signals.
The CMD and SIO0 signals are inputs which receive infor-
mation transmitted by a controller or by another RDRAM’s
SIO1 output. SCK is the CMOS clock signal driven by the
controller. All signals are high true.
The cycle time, high phase time, and low phase time of the
SCK clock are t
SCK
CMD
t
SIO0
DR1
t
DF2
CYCLE1
t
DF1
, t
CH1
and t
t
CL1
DR2
Figure 56: CMOS Timing - Data Signals for Receive
, all measured at the
t
DR2
t
DF2
t
CYCLE1
t
CH1
Page 50
50% level. The rise and fall times of SCK, CMD, and SIO0
are t
The CMD signal is sampled twice per t
the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is t
SCK and CMD timing points are measured at the 50% level.
The SIO0 signal is sampled once per t
falling edge. The set/hold window of the sample points is
t
50% level.
S2
t
t
S1
S2
/t
even
H2.
DR1
The SCK and SIO0 timing points are measured at the
and t
t
t
H1
H2
DF1
, measured at the 20% and 80% levels.
t
CL1
Rev. 1.01 Oct. 1999
t
S1
Direct RDRAM
odd
t
CYCLE1
H1
CYCLE1
S1
interval on the
interval, on
/t
V
V
V
V
V
V
H1.
IH,CMOS
IH,CMOS
IH,CMOS
IL,CMOS
IL,CMOS
IL,CMOS
80%
50%
20%
80%
50%
20%
80%
50%
20%
The
™