tc59lm913amg TOSHIBA Semiconductor CORPORATION, tc59lm913amg Datasheet - Page 42

• Manufacturer Part Number: tc59lm913amg
• Description: 512mbits Network Fcram1 Sstl_2 Interface ? 4,194,304-words ? 8 Banks ? 16-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

•
•
bits in the sequence shown as the following.
Addressing sequence of Sequential mode (A3)
address input to the device.
Addressing sequence of Interleave mode
(R-3) CAS Latency field (A6 to A4)
(R-4) Test Mode field (A7)
(R-5) Reserved field in the Regular Mode Register
CAS Latency = 4
Command
A column access is started from the inputted lower address and is performed by interleaving the address
A column access is started from the inputted lower address and is performed by incrementing the lower
L/UDQS
CLK
CLK
RDA command to the first data read. The minimum values of CAS Latency depends on the frequency
of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
•
DQ
This field specifies the number of clock cycles from the assertion of the LAL command following the
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
Reserved bits (A8 to A13, BA2)
These bits are reserved for future operations. They must be set to “0” for normal operation.
Data 0
Data 1
Data 2
Data 3
DATA
Data 0
Data 1
Data 2
Data 3
DATA
RDA
A6
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
ּּּA8 A7 A6 A5 A4 A3 A2 A1
ּּּA8 A7 A6 A5 A4 A3 A2
ּּּA8 A7 A6 A5 A4 A3 A2
0
0
0
0
1
1
1
1
ACCESS ADDRESS
Addressing sequence for Sequential mode
Addressing sequence for Interleave mode
LAL
n + 1
n + 2
n + 3
A5
N
0
0
1
1
0
0
1
1
ACCESS ADDRESS
A4
0
1
0
1
0
1
0
1
2 words (address bits is LA0)
not carried from LA0~LA1
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
A
A
1
1
BURST LENGTH
CAS LATENCY
A
A0
A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
4
BURST LENGTH
2 words
4 words
TC59LM913AMG-50
Data
0
2005-11-08 42/46
Data
1
Data
2
Data
Rev 1.1
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