tc59lm836dkb TOSHIBA Semiconductor CORPORATION, tc59lm836dkb Datasheet - Page 58

• Manufacturer Part Number: tc59lm836dkb
• Description: 288mbits Network Fcram2 ? 2,097,152-words ? 4 Banks ? 36-bits
• Manufacturer: TOSHIBA Semiconductor CORPORATION

BOUNDARY SCAN TEST ACCESS PORT OPERATIONS
1149.1 – 1990, but which does not implement all the functions required for 1149.1 – 1990. TCK must be tied to V
or V
Test Access Port Signals
Test Access Port Registers
TAP Controller Instruction Set
The TC59LM836DKB has a serial boundary scan test access port (TAP) which is compatible with IEEE Standard
Note: The first bit to be scanned into TDI is taken to be the least significant bit (IR0).
Instruction Register
Test Data Register
DD
IR2
0
0
0
0
1
1
1
1
to disable the TAP when TAP operation is not required.
ID Register
Bypass Register
Boundary Scan Register
SYMBOL
TCK
TMS
TDO
TDI
REGISTER
IR1
0
0
1
1
0
0
1
1
Test Clock Input
Test Mode Select Input
Test Data Input
Test Data Output
IR0
1
0
1
0
1
0
1
0
INSTRUCTION
BSR [ 62 : 0 ]
SAMPLE – Z
IDR [ 31 : 0 ]
RESERVED
RESERVED
RESERVED
IR [ 2 : 0 ]
SYMBOL
ID CODE
SAMPLE
BYPASS
EXTEST
BR
All Test Access Port inputs are sampled on the rising edge of TCK. To disable
the TAP, TCK must be tied to V
The signal presented at TMS is sampled on the rising edge of TCK. This input
is internally pulled up so as to recognize a floating input as a logical High
(Test-Logic-Reset).
Values presented at TDI are clocked into the selected register on the rising
edge of TCK. This input is internally pulled up. This enables detection of when
the TDI input to the board is open-circuit.
TDO is the serial output for test instructions and data from the test logic. This
output is controlled by the falling edge of TCK.
LENGTH (bits)
Moves the Preloaded data on to the output pins. Samples the inputs
connected to the BSCs.
Access ID code.
Tristates the RAM outputs and samples the inputs connected to the BSCs.
This instruction is reserved for future use.
Samples the inputs connected to the BSCs. Load the sampled data at I/Os
to the parallel output of the BSCs. Does not affect RAM operation.
This instruction is reserved for future use.
This instruction is reserved for future use.
Bypasses TDI and TDO using the Bypass register.
32
63
3
1
The Instruction register controls five states (EXTEST,
Sample-Z, Sample, Bypass, ID code).
The register includes information on revision number,
organization and TOSHIBA ID number.
The register connects TDI and TDO.
The Boundary Scan register is comprised of boundary scan
cells at each input and I/O pin. The BSCs are serially
connected between TDI and TDO.
DESCRIPTION
SS
DESCRIPTION
or V
DD
DESCRIPTION
TC59LM836DKB-33,-40
.
2005-11-08 58/65
Rev 1.4
SS