tc59lm814 TOSHIBA Semiconductor CORPORATION, tc59lm814 Datasheet
tc59lm814
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tc59lm814 Summary of contents
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... FCRAM containing 268,435,456 memory cells. TC59LM814CTG is organized as 4,194,304-words × 4 banks s× 16 bits, TC59LM806CTG is organized as 8,388,608 words × 4 banks × 8 bits. TC59LM814/06CTG feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM814/06CTG can operate fast core cycle ...
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... UDQS/LDQS (×16) V Power (+2 Ground SS Power (+2 DDQ (for I/O buffer) Ground V SSQ (for I/O buffer) V Reference Voltage REF Not Connected TC59LM814/06CTG-50,-60 PIN ASSIGNMENT (TOP VIEW) TC59LM814CTG TC59LM806CTG DQ0 2 DQ0 DDQ DDQ 2 DQ1 4 NC DQ2 5 DQ1 SSQ ...
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... COUNTER BURST COUNTER Note: The TC59LM806CTG configuration is 4Bank of 32768 × 256 × cell array with the DQ pins numbered DQ0~DQ7. The TC59LM814CTG configuration is 4Bank of 32768 × 128 × cell array with the DQ pins numbered DQ0~DQ15. To each block LATCH COLUMN DECODER ...
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... Differential Clock AC Middle Level ISO PARAMETER −0.3~V −0.3~V −0.3~V MIN 2.35 2.35 /2 × 96% V DDQ + 0.2 V REF −0.1 −0.1 0.4 + 0.35 V REF −0.1 0.7 /2 − 0.2 V DDQ /2 − 0.2 V DDQ TC59LM814/06CTG-50,-60 RATING UNIT −0. 0.3 V DDQ −0.3~3.3 V 0~70 °C −55~150 °C 260 ° ±50 mA (Notes: 1)(Ta = 0°~70°C) TYP. MAX UNIT 2 ...
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... V + 0.9 V with a pulse width ≤ 5 ns. DDQ = −0.9 V with a pulse width ≤ the transmitting device. DDQ ( CLK )} /2 ICK ICK V (min) ISO ISO = 2 MHz 25°C) PARAMETER TC59LM814/06CTG-50,-60 (DC ICK ICK (max) MIN MAX 2.5 4.0 2.5 4.0 4.0 6.0 ...
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... IN DDQ PARAMETER ≤ OUT DDQ = V − 0.4 V DDQ = 0 − 0.4 V DDQ = 0 − 0.4 V DDQ = 0 − 0.4 V DDQ = 0.4 V and TC59LM814/06CTG-50,-60 ,V =2.5V ± 0.15V 0°~70°C) DD DDQ MAX UNIT -50 -60 190 170 MIN MAX UNIT −5 µA 5 −5 µA 5 − ...
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... C 1.3 L -0.5 × t 0.5 × 0.5 0.5 1.5 0.9 0.9 2.0 −0.65 0.65 TC59LM814/06CTG-50,-60 (Notes -60 UNIT MIN MAX 26 0.45 × t CK 0.45 × t CK −0.85 0.85 0.5 −0.85 0.85 −0.85 0.85 0.9 × t 1.1 × − 0.2 + 0.2 ...
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... L 1 16 200 TC59LM814/06CTG-50,-60 (Notes (continued) -60 UNIT NOTES MIN MAX −0.85 −0.85 0.85 2 0.1 1 −0.5 × 0.4 7.8 µs 200 5 5 ...
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... Output IL max Output ∆T (AC))/∆T (DC) and V IH min IL max contains more than one decimal place, the result ns, 0.75 × 3. rounded up to 3.8 ns.) /2 ± 0.2 V from steady state. DDQ TC59LM814/06CTG-50,-60 VALUE UNIT NOTES + 0. REF − 0. REF ...
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... DDQ . REF 2.5V(TYP) 2.5V(TYP) 1.25V(TYP PDA RSC RSC DESL RDA MRS DESL RDA MRS DESL WRA REF op-code op-code EMRS MRS EMRS MRS TC59LM814/06CTG-50,- REFC REFC 200clock cycle(min) DESL WRA REF DESL Normal Operation Auto Refresh cycle Rev 1.2 2005-06-21 10/39 ...
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... IS IH 1st 2nd UA IPW DIPW DIPW TC59LM814/06CTG-50,- Refer to the Command Truth Table (AC (AC Rev 1.2 2005-06-21 11/39 (AC) ID ...
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... IS IH LAL (after RDA) Input (control & addresses) t IPW CAS latency = 3 DQS Hi-Z (output) DQ Hi-Z (output) CAS latency = 4 DQS Hi-Z (output) DQ Hi-Z (output) Note: The correspondence of LDQS, UDQS to DQ. (TC59LM814CTG) TC59LM814/06CTG-50,- DESL t CKQS t t QSLZ CKQS t QSPRE Preamble QSQ QSLZ t ...
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... IS IH LAL (after WRA) Input (control & addresses) t IPW CAS latency = 3 DQS (input) DQ (input) CAS latency = 4 DQS (input) DQ (input) Note: the correspondence of LDQS, UDQS to DQ. (TC59LM814CTG Timing REFI PAUSE XXXX CLK CLK Input (control & addresses) Command Note: “I ” ...
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... Write Timing (x16 device) (Burst Length = 4) CLK CLK Input WRA LAL (control & addresses) CAS latency = 3 LDQS DQ0 ~DQ7 UDQS DQ8 ~DQ15 CAS latency = 4 LDQS DQ0 ~DQ7 UDQS DQ8 ~DQ15 TC59LM814/06CTG-50,-60 DESL DSSK DSSK DSSK DSSK Preamble ...
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... Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and the command table below. Read Command Table COMMAND (SYMBOL) CS RDA (1st) LAL (2nd) H × Notes: 5. For x16 device " Write Command Table • TC59LM814CTG COMMAND (SYMBOL) CS WRA (1st) L LAL (2nd) H • TC59LM806CTG COMMAND (SYMBOL) CS WRA (1st) ...
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... H PD CURRENT CS FN STATE n − × Standby × × Power Down L L × Power Down from REF command. FPDL TC59LM814/06CTG-50,-60 VW1 × × A6~A0 × × × BA1~BA0 A14~ A6~A0 NOTES × × × × ...
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... H SELFX × × L TC59LM814/06CTG-50,-60 ACTION NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State Begin Read Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh Entry ...
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... Reserved Reserved 1 *2 Reserved *4 *4 BA0 A14~ OUTPUT DRIVE IMPEDANCE CONTROL (DIC TC59LM814/06CTG-50,- A6~ BURST TYPE (BT) 0 Sequential 1 Interleave A1 A0 BURST LENGTH (BL Reserved Reserved × ...
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... STANDBY (IDLE) WRA RDA ACTIVE ACTIVE (RESTORE) LAL WRITE READ (BUFFER) TC59LM814/06CTG-50,-60 POWER DOWN PDEN ( MODE REGISTER MRS LAL Command input Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input. 2005-06-21 19/39 ...
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... RAS RCD cycles I RC DESL RDA LAL = 4 cycles = 1 cycle I I RAS RCD TC59LM814/06CTG-50,- cycles I RC DESL RDA = 4 cycles I RAS cycles I ...
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... I I RAS RCD DQSS DESL WRA LAL = 4 cycles = 1 cycle I I RAS RCD DQSS TC59LM814/06CTG-50,- cycles I RC DESL WRA LAL = 4 cycles I RAS t DQSS DQSS ...
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... I I RAS RCD cycles DESL WRA LAL = 4 cycles = 1 cycle I I RAS RCD TC59LM814/06CTG-50,- cycles I RC DESL RDA LAL = 4 cycles I RAS Hi-Z Hi Hi-Z Hi DQSS Hi-Z Hi Hi-Z Hi ...
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... RDAa LALa = 4 cycles = 1 cycle I I RAS RCD × × Bank “a” Hi-Z Qa0 Qa1 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 TC59LM814/06CTG-50,- cycle cycle I RCD RCD RDAc LALc RDAd LALd RDAb = 2 cycles = 2 cycles ...
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... I RAS RCD × × Bank “a” t DQSS Da0 Da1 Db0 Db1 t t DQSS DQSS Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 TC59LM814/06CTG-50,- cycle = 1 cycle I I RCD RCD WRAc LALc WRAd LALd WRAb = 2 cycles = 2 cycles ...
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... RBD LALb DESL WRAc = 1 cycle I I RCD × Bank “c” t DQSS Da0 Da1 Da2 Da3 Qb0 Qb1 t DQSS Da0 Da1 Da2 Da3 TC59LM814/06CTG-50,- cycles cycles I RWD RDAd LALd DESL WRAc LALc = 1 cycle = 1 cycle I RCD × ...
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... LA=#1 UA UVW=1 LVW=1 Upper byte: Write First One Word Lower byte: Write First One Word Last two data are masked (#1) (#2) Last three data are masked. D0 (#0) (#1) (#2) TC59LM814/06CTG-50,- 5cycles I RC DESL WRA LAL LA=#3 UA VW=2 Last three data are masked. ...
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... DESL QPDH Hi Hi Power Down Entry to maintain the data written into cell. REFI(max) TC59LM814/06CTG-50,- cycles I RSC RDA DESL or WRA × BA, UA Hi-Z Hi-Z n − cycle I PDA RDA × ...
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... DESL = 1 cycle clock cycles Hi-Z Hi Hi-Z Hi Power Down Entry to maintain the data written into cell. REFI(max) TC59LM814/06CTG-50,-60 n − cycle I PDA × DESL t PDEX l t RC(min), REFI(max) Power Down Exit Rev 1.2 2005-06-21 28/ RDA ...
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... I I RAS RCD Hi-Z Hi must be meet 15 clock cycles WRA REF 8 Refresh cycle TC59LM814/06CTG-50,-60 n − cycles I REFC RDA LAL or DESL or MRS or WRA REF WRA REF WRA REF + ...
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... I REFC *5 *5 WRA REF DESL * cycle I RCD I LOCK after PD is brought to “High”. REFC LOCK TC59LM814/06CTG-50,- × (min) and t (max) to Self FPDL FPDL TM , FCRAM perform Auto Refresh and n − − Command (1st) ...
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... LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. TC59LM806CTG TC59LM814CTG CS & FN BA0 Bank #0 0 Bank #1 1 Bank #2 0 Bank #3 1 UPPER ADDRESS A0~A14 A0~A14 TC59LM814/06CTG-50,- competent to BA1 LOWER ADDRESS A0~A7 A0~A6 2005-06-21 31/ Each Rev 1.2 ...
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... V DD DDQ V and V are power supply pins for memory core and peripheral circuits and V are power supply pins for the output buffer. DDQ SSQ REFERENCE VOLTAGE: V REF V is reference voltage for all input signals. REF , SSQ TC59LM814/06CTG-50,-60 Rev 1.2 2005-06-21 32/39 ...
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... Power Down Mode ( PD When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CTG become Power Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers except for PD are disabled after specified time. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to “ ...
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... RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM814/06CTG have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command ...
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... LA1, LA0 not carried from LA1~LA2 ACCESS ADDRESS A5 A4 CAS LATENCY 0 0 Reserved 0 1 Reserved 1 0 Reserved Reserved 1 0 Reserved 1 1 Reserved TC59LM814/06CTG-50,-60 Data Data Data Data BURST LENGTH 2 words 4 words 3 4 Rev 1.2 2005-06-21 35/39 ...
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... Reserved field ( A14) These bits are reserved for future operations and must be set to “0” for normal operation. A1 OUTPUT DRIVER IMPEDANCE CONTROL 0 Normal Output Driver 1 Strong Output Driver 0 Weaker Output Driver 1 Weakest Output Driver TC59LM814/06CTG-50,-60 Rev 1.2 2005-06-21 36/39 ...
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... PACKAGE DIMENSIONS Weight: 0.51 g (typ.) TC59LM814/06CTG-50,-60 Rev 1.2 2005-06-21 37/39 ...
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... Maximum clock cycle time( tCK,max ) of “-50” changed from 8.5ns( 117MHz ) to 12ns( 83MHz ). When t is between 8.5ns and 12ns at “-50” product, all AC timing parameters refered to spec of “-60” CK speed version( page TC59LM814/06CTG-50,-60 Rev 1.2 2005-06-21 38/39 ...
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... The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. TC59LM814/06CTG-50,-60 030619EBA Rev 1.2 2005-06-21 39/39 ...