tc59lm814cft TOSHIBA Semiconductor CORPORATION, tc59lm814cft Datasheet

tc59lm814cft

Manufacturer Part Number

tc59lm814cft

Description

4,194,304 / 8,388,608-words X 4 Banks X 16 / 8-bits Network Fcram

Manufacturer

TOSHIBA Semiconductor CORPORATION

Datasheet

1.TC59LM814CFT.pdf (38 pages)

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4,194,304-WORDS × 4 BANKS × 16-BITS Network FCRAM

8,388,608-WORDS × 4 BANKS × 8-BITS Network FCRAM

DESCRIPTION

FCRAM

bits, TC59LM806CFT is organized as 8,388,608 words × 4 banks × 8 bits. TC59LM814/06CFT feature a fully

synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which

enables high performance and simple user interface coexistence. TC59LM814/06CFT can operate fast core cycle

using the FCRAM

power consumption are required. The Output Driver for Network FCRAM

transfer under light loading condition.

FEATURES

•

Notice: FCRAM is a trademark of Fujitsu Limited, Japan.

Network FCRAM

TC59LM814/06CFT is suitable for Network, Server and other applications where large memory density and low

•

Quad Independent Banks operation

Fast cycle and Short Latency

Bidirectional Data Strobe Signal

Distributed Auto-Refresh cycle in 7.8 µs

Self-Refresh

Power Down Mode

Variable Write Length Control

Write Latency = CAS Latency-1

Programable CAS Latency and Burst Length

Organization

2.5 V CMOS I/O comply with SSTL-2 (half strength driver)

Package:

DD2P

DD6

RAC

DD1S

Fully Synchronous Operation

Fast clock cycle time of 5 ns minimum

Power Supply Voltage V

Clock:

Data:

Burst Length = 2, 4

Double Data Rate (DDR)

Data input/output are synchronized with both edges of DQS.

Differential Clock (CLK and CLK ) inputs

Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .

CS , FN and all address input signals are sampled on the positive edge of CLK.

CAS Latency = 3, 4

Clock Cycle Time (min)

Random Read/Write Cycle Time (min)

Random Access Time (max)

Operating Current (single bank) (max)

Power Down Current (max)

Self-Refresh Current (max)

containing 268,435,456 memory cells. TC59LM814CFT is organized as 4,194,304-words × 4 banks s× 16

200 MHz maximum

400 Mbps/pin maximum

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

TC59LM814CFT: 4,194,304 words × 4 banks × 16 bits

TC59LM806CFT: 8,388,608 words × 4 banks × 8 bits

400 × 875 mil, 66 pin TSOPII, 0.65 mm pin pitch (TSOPII66-P-400-0.65)

PARAMETER

core architecture compared with regular DDR SDRAM.

is Double Data Rate Fast Cycle Random Access Memory. TC59LM814/06CFT are Network

DDQ

: 2.5 V ± 0.15 V

2.5 V ± 0.15 V

CL = 3

CL = 4

190 mA

5.5 ns

25 ns

22 ns

2 mA

3 mA

5 ns

-50

TC59LM814/06

180 mA

27.5 ns

5.5 ns

24 ns

2 mA

3 mA

6 ns

TC59LM814/06CFT-50,-55,-60

-55

is capable of high quality fast data

170 mA

6.5 ns

30 ns

26 ns

2 mA

3 mA

6 ns

-60

2002-08-19 1/38

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