tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet
tc59ym916bkg24a
Manufacturer Part Number
tc59ym916bkg24a
Description
The Second Generation 512-megabit Xdrtm Dram
Manufacturer
ETC-unknow
Datasheet
1.TC59YM916BKG24A.pdf
(76 pages)
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
OVERVIEW
broad range of applications including computer memory, graphics, video, and any other application where high
bandwidth and low latency are required.
Differential Rambus Signaling Level (DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using
conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of
8000/6400/4800 MB/s.
addressed memory transactions. The highly efficient protocol yields over 95% utilization while allowing fine access
granularity. The device's 8 banks support up to four interleaved transactions.
FEATURES
•
• Highest sustained bandwidth per DRAM device
•
•
•
•
Note: XDR is a trademark or a registered trademark in Japan and/or other countries.
The Rambus XDR
The 512Mb Rambus XDR DRAM device is a CMOS DRAM organized as 32M words by 16 bits. The use of
XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly
Highest pin bandwidth available
Low latency
Low power
Programmable I/O width
Lead Free
− 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
− Bi-directional differential RSL (DRSL)
− Programmable on-chip termination
− 8000/6400/4800 MB/s sustained data rate
− 8 banks: bank-interleaved transactions at full bandwidth
− Dynamic request scheduling
− Early-Read-after-Write support for maximum efficiency
− Zero overhead refresh
− 2.0/2.5/3.33 ns request packets
− Point-to-point data interconnect for fastest possible flight time
− Support for low-latency, fast-cycle cores
− 1.8V V
− Programmable small-swing I/O signaling (DRSL)
− Low power PLL/DLL design
− Power Down Self Refresh support
− Per pin I/O Power Down for narrow-width operation
− ×4 / ×8 / ×16 programmable device I/O width
Flexible read/write bandwidth allocation
Minimum pin count
Adaptive impedance matching
Reduced system cost and routing complexity
DD
TM
DRAM device is a general purpose high-performance memory device suitable for use in a
TC59YM916BKG24A,32A,32B,40B,32C,40C
2004-12-15 1/76
Lead Free
Rev 0.1
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