tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 35

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Register Summary
responsible for configuring the component’s operating mode, for managing power state transitions, for managing
refresh, and for managing calibration operations.
Reserved bits must be written as 0 and must be ignored when read. Write-only fields must be ignored when read
This field contains the serial identification value for the device. The value is compared to the SID [5:0] field of a
serial transaction to determine if the serial transaction is directed to this device. The serial identification value is
set during the initialization sequence.
allows the number of DQ/DQN pins used for memory read and write accesses to be adjusted. The SLE field enables
data to be written into the memory through the serial interface using the WDSL register.
is written with a 1, the memory component transitions from Power Down to active state. It is usually unnecessary
to write a 0 into this field; this is done automatically by the PDN command in a COLX packet. The PST field
indicates the current power state of the memory component.
Interface.
read-write and contains the bank address used by self-refresh during the powerdown state. The MBR field controls
how many banks are refreshed during each refresh operation. Figure 24, Figure 25 and Figure 26 show different
fields of the Refresh Row Register (high, middle, and low). This read-write field contains the row address used by
self- and auto-refresh. See “Refresh Transactions” on page 40 for more details.
CCVALUE1 fields, respectively. These are read-write fields which control the amount of IOL current driven by the
DQ and DQN pins during a read transaction. The Current Calibration 0 Register controls the even-numbered DQ
and DQN pins, and the Current Calibration 1 controls the odd-numbered DQ and DQN pins.
ZCVALUE1 fields, respectively. These are read-write fields that control the impedance of the on-chip termination
components in the DQ and DQN pins. The Impedance Calibration 0 Register controls the even-numbered DQ and
DQN pins, and the Impedance Calibration 1 controls the odd-numbered DQ and DQN pins.
PART registers. These are used during device testing. They are not to be read or written during normal operation.
“Timing Parameters” on page 60.
Figure 17 through Figure 40 show the control registers in the memory component. The control registers are
A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray.
Each figure displays the following register information:
1.
2.
3.
4.
5.
6.
Figure 17 shows the Serial Identification register. This register contains the SID [5:0] (serial identification field).
Figure 18 shows the Configuration Register. It contains three fields. The first is the WIDTH field. This field
Figure 19 shows the Power Management Register. It contains two fields. The first is the PX field. When this field
Figure 20 shows the Write Data Serial Load Register. It permits data to be written into memory via the Serial
Figure 23 shows the Refresh Bank Control Register. It contains two fields: BANK and MBR. The BANK field is
Figure 27 and Figure 28 show the Current Calibration 0 and 1 registers. They contain the CCVALUE0 and
Figure 29 and Figure 30 shows the Impedance Calibration 0 and 1 registers. They contain the ZCVALUE0 and
Figure 33 through Figure 39 shows the test registers. This includes the TEST, DLL, PLL0, PLL1, IFT, DA, and
Figure 40 shows the DLY register. This is used to set the value of t
Register name
Register mnemonic
Register address (SADR [7:0] value needed to access it)
Read-only, write-only or read-write
Initialization state
Description of each defined register field
TC59YM916BKG24A,32A,32B,40B,32C,40C
CAC
and t
CWD
used by the component. See
2004-12-15 35/76
Rev 0.1