tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 22

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Memory Operations
Write Transactions
the associated data packets) needed to perform a memory access. The state of the memory core and the address of
the memory access determine how many request packets are needed to perform the access.
row is already present in the sense amp array for the bank). In addition, the selected row for the memory access
matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller.
In this example, the access is made to row Ra of bank Ba.
(activate or precharge) are not needed. A COL packet with WR command to column Ca1 of bank Ba is presented on
edge T
data packets D (a1) and D (a2) follow these COL packets after the write data delay t
separated by the column-cycle time t
already open (a row is already present in the sense amp array for the bank). However, the selected row for the
memory access does not match the address of the row already sensed (a page miss). This comparison must be done
in the memory controller. In this example, the access is made to row Ra of bank Ba, and the bank contains a row
other than Ra.
the present row (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is
presented on edge T
A COL packet with WR command to column Ca1 of bank Ba is presented on edge T
COL packet with WR command to column Ca2 of bank Ba is presented on edge T
and D (a2) follow these COL packets after the write data delay t
column-cycle time t
already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this
case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the
access is made to row Ra of bank Ba.
access the requested row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T
COL packet with WR command to column Ca1 of bank Ba is presented on edge T
COL packet with WR command to column Ca2 of bank Ba is presented on edge T
and D (a2) follow these COL packets after the write data delay t
column-cycle time t
necessary to close the present row (precharge). A precharge command (PRE to bank Ba) is presented on edge T
time t
is made by the memory controller and its page policy.
previous example except that only a single write command is presented, rather than two write commands. This
example shows that even with a minimum length write transaction, the t
The t
time interval is also constrained by the sum t
constraints (t
length (the number of write commands issued between the activate and precharge commands), and the t
parameter could become a constraint for write transactions for future speed bins. In this example, the sum t
+ t
Figure 9 shows four examples of memory write transactions. A transaction is one or more request packets (and
The first timing diagram shows a page-hit write transaction. In this case, the selected bank is already open (a
In this case, write data may be directly written into the sense amp array for the bank, and row operations
The second timing diagram shows an example of a page-miss write transaction. In this case, the selected bank is
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to close
The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is
In this case, write data may not be directly written into the sense amp array for the bank. It is necessary to
The fourth timing diagram shows another example of a page−empty write transaction. This is similar to the
WRPs
RAS
WRP
0
, and a second COL packet with WR command to column Ca2 of bank Ba is presented on edge T
is greater than t
measures the minimum time between an activate command and a precharge command to a bank. This
after the last COL packet with a WR command. The decision whether to close the bank or leave it open
RAS
and t
CC
CC
0
. An activate command (ACT to row Ra of bank Ba) is presented on edge T
. This is also the length of each write data packet.
. This is also the length of each write data packet. After the final write command, it may be
RCD
RAS
−
W
by the amount ∆t
+ t
WRP
CC
) will be a function of the memory device’s speed bin and the data transfer
. This is also the length of each write data packet.
RCD
RAS
TC59YM916BKG24A,32A,32B,40B,32C,40C
−
W
.
+ t
WRP
which will be larger for a write transaction. These two
CWD
CWD
. The two COL packets are separated by the
. The two COL packets are separated by the
RAS
parameter will not be a constraint.
9
1
3
. Two write data packets D (a1)
. Two write data packets D (a1)
a time t
7
CWD
a time t
. The two COL packets are
RCD
2004-12-15 22/76
RCD-W
−
6
W
a time t
later. A second
later. A second
Rev 0.1
2
. Two write
RAS
RP
later.
RCD
0
. A
14
−
W
a