tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 3

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

General Description
of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11…RQ0 request pins, and
DQ15…DQ0/DQN15...DQN0 data pins. The “N” appended to a signal name denotes the complementary signal of a
differential pair.
the signals of a bus. There are two buses that carry packets: the RQ bus and DQ bus. Each packet on the RQ bus
uses a set of 2 bit-windows on each signal, while the DQ bus uses a set of 16 bit-windows on each signal.
(ACT) command. This causes row Ra of bank Ba in the memory component to be loaded into the sense amp array
for the bank. A second request packet at clock edge T
D (a1) at edge T
edge T
to column Ca2. A final request packet at clock edge T
t
the t
Figure 1. XDR DRAM Device Write and Read Transactions
bank Ba of the memory component to load into the sense amp array for the bank. A second request packet at clock
edge T
of the sense amp array for bank Ba. A third request packet at clock edge T
causes the data packet Q (a2) at edge T
contains a PRE command.
t
parameter.
DQN15…0
DQN15…0
RCD-W
RCD-R
DQ15…0
DQ15…0
The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets
A transaction is a collection of packets needed to complete a memory access. A packet is a set of bit windows on
In the write transaction shown in Figure 1, a request packet (on the RQ bus) at clock edge T
The spacing between the request packets are constrained by the following timing parameters in the diagram:
The read transaction shows a request packet at clock edge T
The spacing between the request packets are constrained by the following timing parameters in the diagram:
RQ11
RQ11
…RQ0
…RQ0
CFMN
CFMN
CWRD
CFM
CFM
3
5
, t
, t
contains another write (WR) command. This causes the data packet D (a2) at edge T
t
contains a read (RD) command. This causes the data packet Q (a1) at edge T
RCD-W
T
T
CC
ACT
ACT
CC
a0
a0
0
0
parameter. The spacing of the CFM/CFMN clock edges is constrained by t
, and t
, and t
T
T
WR
1
1
a1
4
Transaction a: WR
to be written to column Ca1 of the sense amp array for bank Ba. A third request packet at clock
Transaction a: RD
t
T
T
CC
RDP
WRP
2
2
t
t
RCD-R
CWD
T
T
. In addition, the spacing between the request and data packets is constrained by the t
WR
3
3
. In addition, the spacing between the request packets and data packets are constrained by
a2
T
T
4
4
D(a1)
T
T
RD
5
5
a1
t
T
T
CC
6
6
D(a2)
t
13
T
T
CAC
RD
7
7
a2
a0 = {Ba, Ra}
a0 = {Ba, Ra}
to also be read from column Ca2. A final request packet at clock edge T
t
WRP
T
T
8
8
t
RDP
T
T
TC59YM916BKG24A,32A,32B,40B,32C,40C
9
9
T
T
1
PRE
13
10
10
a3
contains a write (WR) command. This causes the data packet
contains a precharge (PRE) command.
T
T
11
11
Q(a1)
a1 = {Ba, Ca1}
a1 = {Ba, Ca1}
T
T
12
12
0
containing an ACT command. This causes row Ra of
T
T
PRE
13
13
a3
Q(a2)
T
T
14
14
T
T
7
15
15
contains another RD command. This
T
T
16
16
a2 = {Ba, Ca2}
a2 = {Ba, Ca2}
T
T
17
17
11
CYCLE
T
T
to be read from column Ca1
18
18
T
T
.
6
19
19
2004-12-15 3/76
0
to be also be written
contains an activate
T
T
20
Write Transaction
20
Read Transaction
T
T
a3 = {Ba}
a3 = {Ba}
21
21
Rev 0.1
T
T
t
t
CYCLE
CYCLE
22
22
T
T
CAC
23
23
10