ak5702 AKM Semiconductor, Inc., ak5702 Datasheet - Page 41

• Manufacturer Part Number: ak5702
• Description: 4-channel Adc With Pll & Mic-amp
• Manufacturer: AKM Semiconductor, Inc.

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When ALCA bit = “1”, ALC operation is done for 2ch of ADCA. When ALCB bit = “1”, ALC operation is done for 2ch
of ADCB. Volumes of Lch and Rch always change in common during ALC operation. When ALC4 bit = “0”, ALCA bit
= ALCB bit = “1”, ALC of ADCA and ADCB operate at the individual. When ALC4 bit = “1”, regardless of the setting
of ADCA bit and ADCB bit ,ALC operation is done for 4ch of ADCA and ADCB. Volumes of 4ch always change in
common during 4ch Link ALC operation. During the 4ch Link ALC operation, the setting of ADCA resisters
(LMTHA1-0, ZELMNA, LMATA1-0, ZTMA1-0, WTMA2-0, RGA1-0, REFA7-0, RFSTA1-0) are reflected to the
setting of 4ch Link ALC resister, the set of ADCB (LMTHB1-0, ZELMNB, LMATB1-0, ZTMB1-0, WTMB2-0,
RGB1-0, REFB7-0, RFSTB1-0) resisters are ignored.
1. ALC Limiter Operation
During the 2ch Link ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 28),
the IVA/BL and IVA/BR values (same value) are attenuated automatically by the amount defined by the ALC limiter
ATT step (Table 29). During the 4ch Link ALC limiter operation, when even one of 4 channels of ADCA and ADCB
exceeds the ALC limiter detection level (Table 28), the IVL and IVR values (same value) are attenuated automatically by
the amount defined by the ALC limiter ATT step.
When ZELMNA/B bit = “0” (zero cross detection is enabled), the IVA/BL and IVA/BR values are changed by ALC
limiter operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTMA/B1-0 bits
set the zero crossing timeout periods of both ALC limiter and recovery operation (Table 30). When LFST bit = “1”, if
output level exceeds FS, volume is change to 1 step (Lch and Rch are change to same value) immediately (period: 1/fs), if
output level dosen’t exceed FS, volume is change to 1 step at the individual zero crossing points of Lch and Rch or at the
zero crossing timeout. When LFST bit = “1”, LMATA/B 1-0 bits are recommended to set “00”.
When ZELMNA/B bit = “1” (zero cross detection is disabled), IVA/BL and IVA/BR values are immediately (period:
1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMATA/B1-0 bits.
The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 27)
or less. After completing the attenuation operation, unless operation is changed to manual, the operation repeats when the
input signal level exceeds LMTHA/B1-0 bits.
MS0623-E-00
LMTHA/B1
ALC Operation
Note. ALC4 bit should be changed after ALCA=ALCB bits =“0” or PMADAL=PMADAR= PMADBL=PMADBR
0
0
1
1
bits = “0”. When ALC4 bit= “1”, only either ADCA or ADCB should not be powered-down.
LMTHA/B0
Mode
0
1
2
3
4
0
1
0
1
Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level
ALC4
0
0
0
0
1
ALC Limier Detection Level
ALC Output ≥ −2.5dBFS
ALC Output ≥ −4.1dBFS
ALC Output ≥ −6.0dBFS
ALC Output ≥ −8.5dBFS
ALCB
0
0
1
1
x
ALCA
0
1
0
1
x
Table 27. ALC mode
ALCB Operation
- 41 -
2ch Link
2ch Link
4ch Link
Manual
Manual
ALC Recovery Waiting Counter Reset Level
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
ALCA Operation
2ch Link
2ch Link
4ch Link
Manual
Manual
(default)
[AK5702]
(default)
2007/06