ak5702 AKM Semiconductor, Inc., ak5702 Datasheet - Page 71

• Manufacturer Part Number: ak5702
• Description: 4-channel Adc With Pll & Mic-amp
• Manufacturer: AKM Semiconductor, Inc.

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MS0623-E-00
& Addr:03H, D1-0)
ALC Control 2
ALC Control 1
Timer Control
ADC Internal
MIC Control
MIC Input Recording (Stereo)
(Addr:05H, D3-0)
PMADL/R bit
(Addr:00H, D1-0)
<Example>
(Addr:02H, D4
ALC State
FS3-0 bits
(Addr:0CH)
(Addr:0AH)
(Addr:0BH)
This sequence is an example of ALCA setting at fs=44.1kHz. If the parameter of the ALCA is changed, please refer
to Figure 43.
State
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bit). When the AK5702 is PLL mode, MIC and ADCA should be
(2) Set up MIC input (Addr: 02H&03H)
(3) Set up Timer Select for ALCA (Addr: 0AH)
(4) Set up REF value for ALCA (Addr: 0BH)
(5) Set up LMTHA1-0, RGA1-0, LMATA1-0 and ALCA bits (Addr: 0CH)
(6) Power Up MIC and ADCA: PMADAL = PMADAR bits = “0” → “1”
(7) Power Down MIC and ADCA: PMADAL = PMADAR bits = “1” → “0”
(8) ALCA Disable: ALCA bit = “1” → “0”
When the registers for the ALC operation are not changed, ALCA bit may be keeping “1”. The ALCA operation
is disabled because the MIC&ADCA block is powered-down. If the registers for the ALCA operation are also
changed when the sampling frequency is changed, it should be done after the AK5702 goes to the manual mode
(ALC bit = “0”) or MIC&ADCA block is powered-down (PMADAL=PMADAR bits = “0”). IVOL gain is not
reset when PMADAL=PMADAR bits = “0”, and then IVOL operation starts from the setting value when
PMADAL or PMADAR bit is changed to “1”.
powered-up in consideration of PLL lock time after a sampling frequency is changed.
The initialization cycle time of ADCA is 3088/fs=70.0ms@fs=44.1kHz, HPFA1-0 bits = “00”.
After the ALCA bit is set to “1” and MIC&ADC block is powered-up, the ALCA operation starts from IVOL
default value (0dB).
To start the recording within 100ms, the following sequence is required.
(6a) PMVCM=PMMPA bits = “1”.
(6b) Wait for 2ms, then PMPLL bit = “1”.
(6c) Wait for 6ms, then PMADAL=PMADAR bits = “1”.
X,XXX
0, 01
XXH
XXH
XXH
(1)
ALC Disable
Power Down
(2)
(3)
(4)
(5)
Figure 64. MIC Input Recording Sequence
(6)
Initialize Normal State Power Down
3088 / fs
ALC Enable
1111
1, 01
0AH
E1H
81H
- 71 -
(7)
ALC Disable
(8)
01H
Example:
PLL Master Mode
Audio I/F Format:I2S
Pre MIC AMP:+15dB
MIC Power On
Sampling Frequency:44.1kHz
ALCA bit = “1”
ALC setting:Refer to Figrure 45
(1) Addr:05H, Data:2FH
(3) Addr:0AH, Data:0AH
(4) Addr:0BH, Data:E1H
(5) Addr:0CH, Data:81H
(2) Addr:02H, Data:10H
(6) Addr:00H, Data:07H
(8) Addr:0CH, Data:01H
(7) Addr:00H, Data:04H
Addr:03H, Data:01H
Recording
[AK5702]
2007/06