xr16v564 Exar Corporation, xr16v564 Datasheet - Page 33

• Manufacturer Part Number: xr16v564
• Description: 2.25v To 3.6v Quad Uart With 32-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.1
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL
input, see below table for details. This bit is also used to control the OP2# signal during internal loopback
mode. INTSEL pin must be LOW during 68 mode.
•
•
MCR[4]: Internal Loopback Enable
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•
MCR[5]: Xon-Any Enable (requires EFR bit-4 = 1)
•
•
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4 = 1)
•
•
MCR[7]: Clock Prescaler Select (requires EFR bit-4 = 1)
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•
Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During internal loopback mode,
OP2# is HIGH.
Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During internal loopback mode, OP2# is LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the V564 is programmed to use the Xon/Xoff flow control.
Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be LOW during idle data conditions.
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
INTSEL
P
0
0
1
IN
MCR
B
T
IT
0
1
X
ABLE
-3
14: INT O
INT A-D O
33
UTPUT
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
Three-State
UTPUTS IN
Active
Active
M
ODES
Figure
16 M
ODE
13.
XR16V564/564D