xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 20

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

XR16C872
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the internal registers. UART A and B has same
register set independently control. The assigned bit functions are defined in the following paragraphs.
UART INTERNAL REGISTERS
Rev. 1.00
Basic Registers are accessible when LCR bit-7 is set to logic 0.
Baud Rate Generator Registers are accessible only when LCR bit-7 is set to a logic 1.
A2 A1 A0
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8 9 0
SPR [FF] or
FIFO Count
MCR [00]
MSR [00]
Register
[Default]
RHR [XX]
FCR [00]
DLM [XX]
THR [XX]
LCR [00]
LSR [60]
DLL [XX]
IER [00]
ISR [01]
Note *3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
interrupt
enabled
FIFO’s
(MSB)
enable
RCVR
trigger
divisor
select
CTS#
Clock
BIT-7
bit-15
FIFO
latch
bit-7
bit-7
error
CD#
bit-7
bit-7
0/
0/
0/
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
interrupt
shift reg.
enabled
FIFO’s
enable
RCVR
trigger
empty
trans.
BIT-6
RTS#
(LSB)
break
bit-14
IRRT
bit-6
bit-6
bit-6
bit-6
RI#
set
0/
0/
0/
DISCONTINUED
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
reg. empty
interrupt
Xon-Any
holding
trigger
(MSB)
RTS#,
DSR#
BIT-5
CTS#
parity
trans.
bit-13
Xoff
bit-5
bit-5
bit-5
0/TX
bit-5
set
0/
0/
0/
20
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
1 2 3 4 5 6 7
interrupt
trigger
Sleep
mode
(LSB)
BIT-4
parity
break
CTS#
bit-12
back
bit-4
bit-4
0/TX
even
bit-4
Det.
loop
bit-4
Xoff
0/
0/
Visit Exar Web Site at www.exar.com
interrupt
modem
framing
(OP2#)
status
priority
enable
select
BIT-3
mode
parity
bit-11
DMA
delta
bit-2
error
CD#
bit-3
bit-3
bit-3
bit-3
int
(Shaded bits are enabled by EFR bit-4)
interrupt
receive
(OP1#)
status
priority
BIT-2
parity
bit-10
XMIT
FIFO
reset
delta
error
bit-2
bit-2
bit-2
bit-1
stop
bit-2
line
bits
RI#
int
transmit
register
holding
overrun
priority
RCVR
length
DSR#
BIT-1
RTS#
FIFO
reset
word
delta
bit-1
bit-1
bit-0
bit-1
error
bit-1
bit-1
bit-9
int
register
holding
receive
receive
enable
status
length
BIT-0
DTR#
ready
CTS#
FIFO
delta
word
bit-0
bit-0
bit-0
bit-0
data
bit-0
bit-8
int