xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 25

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

TRIGGER TABLE-D (Transmit)
FCR BIT 6-7: (logic 0 or cleared is the default condition,
RX trigger level =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The interrupt will trigger again
when RX data got unloaded below the threshold and
incoming data fill it back up to the trigger level. The FCTR
Bits 4-5 selects one of the following table.
TRIGGER TABLE-A (Receive)
“Default setting after reset, ST16C550 mode”
TRIGGER TABLE-B (Receive)
TRIGGER TABLE-C (Receive)
BIT-7
BIT-5
BIT-7
BIT-7
Rev. 1.00
X
0
0
1
1
0
0
1
1
0
0
1
1
BIT-6
BIT-6
BIT-6
BIT-4
X
0
1
0
1
0
1
0
1
0
1
0
1
User programmable
FIFO trigger level
FIFO trigger level
FIFO trigger level
FIFO trigger level
trigger levels
14
16
24
28
16
56
60
1
4
8
8
8
DISCONTINUED
25
TRIGGER TABLE-D (Receive)
An example to program the FIFO trigger level:
write LCR with 0xBF
set FCTR bit4-5 to logic 1 ; select trigger Table-D
set FCTR bit-7 to logic 0
write TRG with 0x60
set FCTR bit-7 to logic 1
write TRG with 0x08
write LCR with 0x03
Receive data ready interrupt will activates when RX FIFO fills up to
96 data bytes while the transmit empty interrupt gets set when
data is empty to 8 bytes.
BIT-7
X
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BIT-6
X
; point to enhanced registers
; program RX FIFO trigger level
; set your RX trigger level to 96
; program TX FIFO trigger level
; set your TX trigger level to 8
; set operating parameters
User programmable
FIFO trigger level
XR16C872
trigger levels