xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 26

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

XR16C872
Interrupt Status Register (ISR)
The UART provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status
Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the
user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However it should
be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after re-
reading the interrupt status bits. The Interrupt Source Table 6 (below) shows the data values (bit 0-5) for the six
prioritized interrupt levels, the interrupt sources associated with each of these interrupt levels, and how to clear each
interrupt (INT).
ISR BIT-0:
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service
routine.
Logic 1 = No interrupt pending. (normal default condition)
ISR BIT 1-3: (logic 0 or cleared is the default condition)
These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (See Interrupt Source
Table).
ISR BIT 4-5: (logic 0 or cleared is the default condition)
These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that matching Xoff character(s) have
been received. ISR bit-5 indicates that CTS# or RTS# condition have changed. Note that once set to a logic 1, the
ISR bit-4 will stay a logic 1 until Xon character(s) is received or upon a read to register ISR.
ISR BIT 6-7: (logic 0 or cleared is the default condition) These bits are set to a logic 0 when the FIFO is not being
used. They are set to a logic 1 when the FIFOs are enabled
Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication format. The word length, the
number of stop bits, and the parity are selected by writing the appropriate bits in this register. This register also has
a secondary function to select 2 other register sets. The first is by setting bit-7 = 1 to select the baud rate divisor
(DLL and DLM) registers, and the second set of registers is selected when a “BF” hex is written to LCR to select
the enhanced register set.
Priority
Level
Rev. 1.00
1
2
2
3
4
5
6
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt
0
0
0
0
0
0
1
0
0
0
0
0
1
0
[ ISR BITS ]
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
Table 4, Interrupt Priority and Source
0
0
0
0
0
0
0
DISCONTINUED
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time out)
TXRDY ( Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Rcv. Xoff signal / Special character)
CTS, RTS change of state
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INT clears
LSR read
LSR read
LSR read
ISR read
MSR read
ISR read
MSR read
after a