xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 5

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

PIN DESCRIPTION
Signal Type Definition. The following signal type definitions are from the 872 device point of view.
HOST INTERFACE
A0-A15
Name
D0-D7
AEN
IOR#
IOW#
IRQ15
IRQ12-10
IRQ9
IRQ3-7
DREQ5
DREQ3
DREQ1
DREQ0
DACK5#
DACK3#
DACK1#
DACK0#
Rev. 1.00
I
O
OT24
IOP14
IO24
Standard input
Standard active output
Tri-state output
Tri-state bi-directional input/output
Tri-state bi-directional input/output
Pin #
30-21
92-96
17,18
87-89
2-15
100
19
99
86
97
78
79
80
81
82
83
84
85
Type
OT24
OT24
IO24
I
I
I
I
I
ISA Bus Address. All 16 bits are used during PnP auto configuration
manual configuration mode A0-A10 are used for decoding COM1-4 and
LPT1-2 addresses. After auto or manual configuration, bits A0-A2 select
UART internal registers and A3-A10 are used to select UART A or B, or
the 1284 printer port.
ISA Data Bus. These are the eight three state data lines for transferring
data to or from the controlling CPU. D0 is the least significant bit and the
first data bit in a transmit or receive serial data stream.
Address Enable. Active high to validate A0-A15 address lines during Direct
Memory Access operation on the ISA bus. Connect to logic 0 when it is not used.
Read Strobe. A logic 0 transition on this pin will request the contents of
an Internal register defined by address bits A0-A2 for either UART channels
A/B or A0-A1 for the printer port, be place onto D0-D7 data bus for a read
cycle by the CPU.
Write Strobe. A logic 1 transition on this pin will transfer the data on the
data bus (D0-D7), as defined by either address bits A0-A2 for UART channels
A/B or A0-A1 for the printer port, into an internal register during a write cycle
from the CPU.
Interrupt Request Lines. These are three state active high interrupt lines to
controlling CPU when an interrupt request is generated by the UART
channel A/B or 1284 printer port.
DMA Request Channel 0,1,3 and 5. These are three state active high
outputs with internal weak pull down resistor. DMA request is used
by the 1284 parallel port during ECP and FIFO mode.
DMA Acknowledge Channel 0,1,3 and 5. These are active low inputs
and are used by the 1284 parallel port during ECP and FIFO mode.
sequence with external EEPROM providing the resource data. In the
DISCONTINUED
5
Pin Description
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XR16C872