xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 31

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

EFR BIT-4:
Enhanced function control bit. The content of the IER
bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7
can be modified and latched. After modifying any bits in
the enhanced registers, EFR bit-4 can be set to a logic
0 to latch the new values. This feature prevents existing
software from altering or overwriting the UART enhanced
functions.
Logic 0 = disable/latch enhanced features. IER bits 4-
7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are saved
to retain the user settings, then IER bits 4-7, ISR bits 4-
5, FCR bits 4-5, and MCR bits 5-7 are initialized to the
default values shown in the Internal Resister Table. After
a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with
ST16C550 mode. (normal default condition).
Logic 1 = Enables the enhanced functions. When this
bit is set to a logic 1 all enhanced features of the UART
are enabled and user settings stored during a reset will
be restored.
EFR BIT-5:
Logic 0 = Special Character Detect Disabled (normal
default condition)
Logic 1 = Special Character Detect Enabled. The UART
compares each incoming receive character with Xoff-2
data. If a match exists, the received data will be
transferred to FIFO and ISR bit-4 will be set to indicate
detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character.
When this feature is enabled, the normal software flow
control must be disabled (EFR bits 0-3 must be set to
a logic 0).
EFR BIT-6:
Automatic RTS is used for hardware flow control by
enabling EFR bit-6. The user must assert RTS# to
initiate this function. When AUTO RTS is selected, an
interrupt will be generated when the receive FIFO is filled
to the programmed RX trigger level and RTS# will go to
a logic 1 when it reaches the upper limit of the hysteresis
level. RTS# will return to a logic 0 when data is unloaded
to the lower limit of the hysteresis. The state of this
register bit changes with the status of the hardware flow
control. RTS# functions normally when hardware flow
control is disabled.
Rev. 1.00
DISCONTINUED
31
0 = Automatic RTS flow control is disabled. (normal
default condition)
1 = Enable Automatic RTS flow control.
EFR bit-7:
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(normal default condition)
Logic 1 = Enable Automatic CTS flow control. Transmis-
sion stops when CTS# goes to a logical 1. Transmission
resumes when the CTS# pin returns to a logical 0.
FEATURE CONTROL REGISTER (FCR)
This register is only accesible when LCR is set to 0xBF.
FCTR BIT 0-1:
User selectable RTS# delay or hysteresis for hardware
flow control application. After reset, these bits are set to
logic 0 to select the next trigger level on the RX FIFO
trigger level (FCR bit 6-7,Table-A). These bits are also
associated with EMSR bit-4 and 5 for the hysteresis
control. See EMSR register for more details.
FCTR BIT-2:
0 = Select RX input as encoded IrDa data.
1 = Select RX input as active high encoded IrDa data.
FCTR BIT-3:
Auto RS485 Half Duplex Direction control.
*OP1# output is not available in the 872, however, it does
change the behavior of the transmit empty interrupt.
0 = Transmitter generates an interrupt when transmit
holding register becomes empty while transmit shift
register is still shifting data out.
1 = Enable Auto RS485 Half Duplex Direction Control.
The transmit empty interrupt generation is delayed until
the Transmitter Shift Register (TSR) becomes empty.
FCTR BIT 4-5:
Transmit / receive trigger table select.
FCTR
Bit-5
0
0
1
1
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FCTR
Bit-4
0
1
0
1
Table-D (TX/RX)
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
XR16C872
Trigger
Table