xr16c872iq Exar Corporation, xr16c872iq Datasheet - Page 34

• Manufacturer Part Number: xr16c872iq
• Description: Dual Uart With 1284 Parallel Port And Plug-and-play Controller
• Manufacturer: Exar Corporation

XR16C872
1284 Controller
The bi-directional parallel data port controller is compatible to IEEE Standard 1284 interface. The 1284 interface
can be programmed as a standard printer port or bi-directional parallel port for high speed data transfer systems.
The 1284 interface provides 1284 Level II electrical interface, needing no external transceivers to interface to the
parallel port cable. Hence, it can connect directly to a printer or a high speed bi-directional parallel device. The 1284
controller supports the following modes of operation.
On a reset, the device defaults to compatible mode which is the standard PC Centronics printer mode in PC
computers. The EPP, and ECP modes can only be activated by programming the Extended Control Register (ECR),
this requires address bit A10=1, which is outside the normal parallel port address in the ISA I/O space. The internal
timing is designed to operate from a 22.1184 MHz clock which is supplied from an external source on pin XTAL1
or by the built-in oscillator circuit with an appropriate crystal.
Optional capabilities of the ECP specification are set as follows:
Rev. 1.00
Standard Centronics interface, forward only
Bi-directional Centronics.
Parallel port with data FIFO.
ECP, Extended Capabilities Port, and with 16 byte data FIFO in Forward and Reverse modes, supports
Run Length Encoded (RLE) de-compression in the reverse mode, however, no compression is sup-
ported in the forward mode, and Direct Memory Access transfer capability.
EPP, Enhanced Parallel Port.
ECP defined interrupts are pulsed, low true (Centronics ACK# is non-pulsed, low true).
PWord size is forced to 1 byte.
There is 1 byte in the transmitter that does not
RLE compression is not supported in hardware.
IRQ channel is selectable as 5, 7, or 9.
DMA channel is selectable as 3
FIFO THRESHOLD is set at 8 (used only for non-DMA access to the FIFO).
PORT
DATA
ECP-AFIFO
DSR
DCR
EPP-APort
EPP-DPort
C-FIFO
ECP-DFIFO
T-FIFO
Cnfg-A
Cnfg-B
ECR
ADDRESS
004-007
001
002
400
400
401
402
000
000
003
400
400
Read/Write
R-R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
R
DISCONTINUED
MODE
000
011
100
100
010
011
110
111
111
34
All
All
All
affect the FIFO full bit (ECP modes).
FUNCTION
Data port
Status Register
Control Register
EPP Port (Data)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
ECP FIFO (Address)
EPP Port (Address)
Parallel Port Data FIFO
ECP FIFO (Data)
Visit Exar Web Site at www.exar.com