xr17l152im Exar Corporation, xr17l152im Datasheet - Page 27

• Manufacturer Part Number: xr17l152im
• Description: 3.3v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
T
A
ABLE
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
A3-A0
DDRESS
11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
TXTRG
RXCNT
RXTRG
TXCNT
FCTR
N
RHR
MCR
MSR
MSR
THR
DLM
FCR
SPR
R
LCR
LSR
EFR
DLL
IER
ISR
AME
EG
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EAD
RITE
W
W
W
W
W
R
R
R
R
R
/
Auto CTS/
DSR# Int.
Prescaler
RX FIFO
RX FIFO
Enable
Enable
Trigger
Divisor
Enable
E
RS485
Enable
FIFOs
DLY-3
B
CTS/
Table
BRG
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
TRG
DSR
Bit-7
Bit-7
Bit-7
Bit-7
RROR
Bit-1
CD
IT
0/
0/
-7
Auto RTS/
DTR# Int.
RX FIFO
Enable
Enable
Trigger
Set TX
Enable
RS485
Enable
FIFOs
Empty
Break
DLY-2
B
Table
RTS/
TRG
Bit-6
Bit-6
Bit-6
Bit-6
TSR
Bit-6
DTR
Bit-6
Bit-6
Bit-6
Bit-6
Bit-0
IT
IR
RI
0/
0/
-6
Set Parity Even Par-
Xon/Xoff/
Sp. Char.
Flow Cntl
TX FIFO
XonAny
Special
Enable
Trigger
RS485
RS485
Enable
Empty
Select
Delta-
DLY-1
B
DSR
Char
Bit-5
Bit-5
Bit-5
Bit-5
THR
Bit-5
Auto
Bit-5
Bit-5
Bit-5
Bit-5
Int.
IT
0/
0/
0/
0/
-5
27
RS485 DLY-
MCR[7:5,2]
RX Break
FCR[5:4],
IER [7:5],
ISR [5:4],
MSR[7:4]
Xoff/spe-
TX FIFO
RX Input
cial char
Lopback
Invert IR
Internal
Enable
Enable
Trigger
B
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
CTS
ity
IT
0/
0/
0
0
-4
Status Int.
RX Fram-
Reserved Reserved Reserved Reserved
RTS/DTR
Hyst Bit-3
Flow Cntl
Software
ing Error
Modem
Source
Enable
Enable
(OP2)
Mode
Parity
B
Delta
DMA
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
INT
IT
-3
1
Status Int.
RTS/DTR
RTS/DTR
Hyst Bit-2
RX Parity
Flow Cntl
Stop Bits
Software
TX FIFO
Flow Sel
RX Line
Source
Enable
(OP1)
Reset
B
Error
Delta
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
INT
RI#
IT
-2
S
1
HADED BITS ARE ENABLED BY
TX Empty
RTS# Pin
RTS/DTR
Hyst Bit-1
RX Over-
Flow Cntl
RX FIFO
Software
Source
Control
Enable
Length
DSR#
Reset
DISCONTINUED
B
Word
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
Int.
IT
-1
DTR# Pin
RTS/DTR
Hyst Bit-0
áç
áç
áç
áç
Flow Cntl
Software
RX Data
RX Data
Source
Control
Enable
Enable
Length
Ready
FIFOs
CTS#
Word
B
Delta
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
Int.
IT
-0
EFR B
User Data
C
LCR[7]=0
LCR[7]=0
LCR[7]=1
LCR[7]=1
OMMENT
IT
-4.