xr17l152im Exar Corporation, xr17l152im Datasheet - Page 30
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xr17l152im
Manufacturer Part Number
xr17l152im
Description
3.3v Pci Bus Dual Uart
Manufacturer
Exar Corporation
Datasheet
1.XR17L152IM.pdf
(55 pages)
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DISCONTINUED
Receive Holding Register (RHR)
The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register
(RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this
register whenever a data byte is transferred from the RSR. The RHR is also part of the receive FIFO of 64
bytes by 11-bit wide, 3 extra bits are for the error tags in LSR. When the FIFO is enabled by FCR bit-0, the
RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is
loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR
bits 1-4.
F
F
4.8
4.7.1
4.7.2
IGURE
IGURE
Receive Data
Byte and Errors
(8 X M O D E R e g is t e r )
16X or 8X Sampling
Clock (8XMODE Reg.)
14. R
15. R
a n d E rr o rs
Registers
D a ta B y te
1 6 X o r 8 X C lo c k
R e c e iv e
Receiver Operation with FIFO
Receiver Operation in non-FIFO Mode
64 bytes by 11-
bit wide FIFO
ECEIVER
ECEIVER
O
O
PERATION IN NON
PERATION IN
L S R b its
T a g s in
Receive Data Shift
E r ro r
Register (RSR)
3 :1
Receive Data
Receive
R e c e iv e D a ta S h ift
(64-byte)
FIFO
FIFO
Data
R e g is te r (R S R )
H o ld in g R e g is t e r
-FIFO M
R e c e iv e D a ta
AND
(R H R )
F
Data falls to 40
FIFO Trigger=48
Data fills to 56
Validation
LOW
Data Bit
ODE
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
C
30
ONTROL
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
V a lid a t io n
D a ta B it
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
M
ODE
R H R I n te r ru p t (IS R b it -2 )
Receive Data Characters
R e c e iv e D a t a C h a ra c te r s
3.3V PCI BUS DUAL UART
RXFIFO1
XR17L152
REV. 1.1.0