xr17l152im Exar Corporation, xr17l152im Datasheet - Page 40

• Manufacturer Part Number: xr17l152im
• Description: 3.3v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

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DISCONTINUED
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input
when the modem interface is not used.
Modem Status Register (MSR) - Write Only
The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around from
transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a
RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last
transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in
long-cable networks.
Scratch Pad Register (SPR)
This is an 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
Feature Control Register (FCTR)
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
T
ABLE
15: A
UTO
Table 15
MSR[7]
RS485 H
0
0
0
0
0
9
0
0
1
1
1
1
1
1
1
1
shows the selection. The bits are enabled by EFR bit-4.
MSR[6]
ALF
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-
DUPLEX
MSR[5]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D
IRECTION
MSR[4]
40
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C
ONTROL
D
ELAY IN
D
ELAY FROM
D
ATA
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
B
IT
T
(
S
RANSMIT
3.3V PCI BUS DUAL UART
) T
IME
-
TO
-R
ECEIVE
XR17L152
REV. 1.1.0