xr17l152im Exar Corporation, xr17l152im Datasheet - Page 9

• Manufacturer Part Number: xr17l152im
• Description: 3.3v Pci Bus Dual Uart
• Manufacturer: Exar Corporation

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
N
The device configuration registers and a special way to access each of the UART’s transmit and receive data
FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating
parameters to the L152 UART and for monitoring the status of various functions. The registers occupy 1K of
PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded
into the Memory Base Address Register (BAR) in the PCI local bus configuration register set. These registers
control or report on both channel UARTs functions that include interrupt control and status, 16-bit general
purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-
reset control, and device identification and revision, and others.
The registers set is mapped into 2 address blocks where each UART channel occupies 512 bytes memory
space for its own 16550 compatible configuration registers. The device configuration and control registers are
embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can
be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host at beginning of the
bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s
address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer
is automatically bumped to the next sequential data location either in byte, word or dword. One special case
applies to the receive data unloading when reading the receive data together with its LSR register content. The
host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated
error tags.
0x000 - 0x00F
0x010 - 0x07F
0x080 - 0x093
0x094 - 0x0FF
0x100
0x100
0x140 - 0x17F
0x180 - 0x1FF
1.2
OTE
O
A
FFSET
DDRESS
0x3C
0x34
0x38
: RWR
Device configuration Register Set
A
DDRESS
1
=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. WO=Write Only.
31:24
23:16
15:8
7:0
31:0
31:0
B
ITS
UART channel 0 Regs
Reserved
DEVICE CONFIG.
REGISTERS
Reserved
UART 0 – Read FIFO
UART 0 – Write FIFO
Reserved
UART 0 – Read FIFO
with status
M
RWR
EMORY
T
RO
RO
RO
RO
RO
T
YPE
ABLE
T
ABLE
S
1: PCI L
PACE
Reserved (returns zeros)
Reserved (returns zeros)
Unimplemented MAXLAT
Unimplemented MINGNT
Interrupt Pin, use INTA#.
Interrupt Line.
2: XR17L152 D
OCAL
(Table 10
R
Read/Write
B
Read-Only
Write-Only
Read-Only
EAD
(Table
US
EVICE
/W
&
C
Table
ONFIGURATION
RITE
3)
9
C
D
ONFIGURATION
11)
ESCRIPTION
D
8/16/24/32
8/16/24/32
8/16/24/32
8/16/24/32
ATA
16/32
S
W
PACE
IDTH
R
EGISTERS
R
EGISTERS
First 8 regs are 16550 compatible
64 bytes of RX FIFO data
64 bytes of TX FIFO data
64 bytes of RX FIFO data + LSR
DISCONTINUED
C
OMMENT
áç
áç
áç
áç
R
0x00000000
0x00000000
ESET
0xXX
(
0x00
0x01
0x00
HEX
V
ALUE
)