sc16c652-04 NXP Semiconductors, sc16c652-04 Datasheet - Page 20

• Manufacturer Part Number: sc16c652-04
• Description: Sc16c652 Dual Uart With 32 Bytes Of Transmit And Receive Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11634
Product data
7.4 Interrupt Status Register (ISR)
The SC16C652 provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits.
“Interrupt source”
levels and the interrupt sources associated with each of these interrupt levels.
Table 14:
Table 15:
Priority
level
1
2
2
3
4
5
6
Bit
7-6
5-4
3-1
0
ISR[5]
0
0
0
0
0
0
1
Interrupt source
Interrupt Status Register bits description
Symbol
ISR[7-6]
ISR[5-4]
ISR[3-1]
ISR[0]
shows the data values (bits 0-3) for the four prioritized interrupt
ISR[4]
0
0
0
0
0
1
0
Rev. 04 — 20 June 2003
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C652 mode.
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
Dual UART with 32 bytes of transmit and receive FIFOs
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
ISR[3]
0
0
1
0
0
0
0
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
ISR[0]
0
0
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Received Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter
Holding Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal) / Special character
CTS, RTS change of state
SC16C652
Table
Table 14
14).
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