sc16c652 NXP Semiconductors, sc16c652 Datasheet - Page 13

• Manufacturer Part Number: sc16c652
• Description: Dual Uart With 32 Bytes Of Transmit And Receive Fifos
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 11634
Product data
Fig 4. Internal loop-back mode diagram.
RXRDYA, RXRDYB
TXRDYA, TXRDYB
INTA, INTB
CSA, CSB
RESET
D0–D7
A0–A2
IOW
IOR
SC16C652
CONTROL LOGIC
INTERRUPT
REGISTER
CONTROL
DATA BUS
SELECT
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the
transmit holding register via the user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the receive UART via the internal
loop-back connection. The receive UART converts the serial data back into parallel
data that is then made available at the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
LOGIC
LOGIC
AND
Rev. 04 — 20 June 2003
Dual UART with 32 bytes of transmit and receive FIFOs
XTAL1
GENERATOR
CLOCK AND
BAUD RATE
TRANSMIT
REGISTER
REGISTER
RECEIVE
FIFO
FIFO
XTAL2
TRANSMIT
REGISTER
REGISTER
RECEIVE
CONTROL
SHIFT
SHIFT
MODEM
LOGIC
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
MCR[4] = 1
002aaa350
SC16C652
TXA, TXB
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
DSRA, DSRB
(OP1A, OP1B)
RIA, RIB
(OP2A, OP2B)
CDA, CDB
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