sc16is850l NXP Semiconductors, sc16is850l Datasheet - Page 29

• Manufacturer Part Number: sc16is850l
• Description: Single Uart With I2c-bus/spi Interface, 128 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16IS850L
Product data sheet
8.10 Scratchpad Register (SPR)
8.12 Transmit FIFO Level Count (TXLVLCNT)
8.13 Receive FIFO Level Count (RXLVLCNT)
8.11 Divisor Latch (DLL and DLM)
8.9 Extra Feature Control Register (EFCR)
This is a write-only register, and it allows the software access to these registers: ‘first extra
feature register set’, ‘second extra feature register set’, Transmit FIFO Level Counter
(TXLVLCNT), and Receive FIFO Level Counter (RXLVLCNT).
Table 20.
Remark: EFCR[2:1] has higher priority than EFCR[0]. TXLVLCNT and RXLVLCNT can
only be accessed if EFCR[2:1] are zeroes.
The SC16IS850L provides a temporary data register to store 8 bits of user information.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM, stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
This register is a read-only register. It reports the number of spaces available in the
transmit FIFO.
This register is a read-only register. It reports the fill level of the receive FIFO (the number
of characters in the RX FIFO).
Bit
7:3
2:1
0
EFCR[7:3]
Symbol
EFCR[2:1]
EFCR[0]
Extra Feature Control Register bits description
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 22 July 2011
Description
reserved
Enable Extra Feature Control bits
Enable TXLVLCNT and RXLVLCNT access
00 = General register set is accessible
01 = First extra feature register set is accessible
10 = Second extra feature register set is accessible
11 = reserved
0 = TXLVLCNT and RXLVLCNT are disabled
1 = TXLVLCNT and RXLVLCNT are enabled and can be read.
Single UART with I
SC16IS850L
2
C-bus/SPI interface
© NXP B.V. 2011. All rights reserved.
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