sc16is850l NXP Semiconductors, sc16is850l Datasheet - Page 7

• Manufacturer Part Number: sc16is850l
• Description: Single Uart With I2c-bus/spi Interface, 128 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
SC16IS850L
Product data sheet
7.1 Extended mode (128-byte FIFO)
Please refer to
The SC16IS850L provides serial asynchronous receive data synchronization,
serial-to-serial data conversions for both the transmitter and receiver sections.
Synchronization for the serial data stream is accomplished by adding start and stop bits to
the transmit data to form a data character (character orientated protocol). Data integrity is
ensured by attaching a parity bit to the data character. The parity bit is checked by the
receiver for any transmission bit errors. The electronic circuitry to provide all these
functions is fairly complex, especially when manufactured on a single integrated silicon
chip. The status of the UART can be read at any time during functional operation by the
host through either I
The SC16IS850L represents such an integration with greatly enhanced features. The
SC16IS850L is fabricated with an advanced CMOS process. The SC16IS850L provides a
single UART capability with 128 bytes of transmit and receive FIFO memory, instead of
64 bytes for the SC16IS750. The SC16IS850L is designed to work with high speed
modems and shared network environments that require fast data processing time.
Increased performance is realized in the SC16IS850L by transmit and receive FIFOs. This
allows the external processor to handle more networking tasks within a given time. In
addition, the four selectable receive and transmit FIFO trigger interrupt levels are provided
in 16C650 mode, or 128 programmable levels are provided in the extended mode for
maximum data throughput performance especially when operating in a multi-channel
environment (see
greatly reduces the bandwidth requirement of the external controlling CPU and increases
performance. Sleep mode function in the SC16IS850L allows the UART to be placed
under low power mode when the serial data input line, RX, is idle, TX FIFO and Transmit
Shift Registers are empty, and there is no interrupt pending except THR. The UART is
capable of operation up to 5 Mbit/s with an external 80 MHz clock. With a crystal, the
SC16IS850L is capable of operation up to 1.5 Mbit/s.
The rich feature set of the SC16IS850L is available through internal registers. These
features are: selectable and programmable receive and transmit FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls, and are all standard
features. Following a power-on reset, an external reset, or a software reset, the
SC16IS850L is software compatible with the previous generation, SC16C550B, and
SC16C650B.
The SC16IS850L has selectable hardware flow control and software flow control.
Hardware flow control significantly reduces software overhead and increases system
efficiency by automatically controlling serial data flow using the RTS output and CTS input
signals. Software flow control automatically controls data flow by using programmable
Xon/Xoff characters. The UART includes a programmable baud rate generator that can
divide the timing reference clock input by a divisor between 1 and (2
The device is in the extended mode when any of these four registers contains any value
other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.
Figure 1 “Block diagram of SC16IS850L I
All information provided in this document is subject to legal disclaimers.
”Section 7.1 “Extended mode (128-byte
2
C-bus or SPI interface.
Rev. 1 — 22 July 2011
Single UART with I
2
C-bus
FIFO)”). The FIFO memory
SC16IS850L
interface”.
2
16
C-bus/SPI interface
 1).
© NXP B.V. 2011. All rights reserved.
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