sc16is850l NXP Semiconductors, sc16is850l Datasheet - Page 9

• Manufacturer Part Number: sc16is850l
• Description: Single Uart With I2c-bus/spi Interface, 128 Bytes Of Transmit And Receive Fifos, Irda Sir Built-in Support
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16IS850L
Product data sheet
7.3.1 32-byte FIFO mode
7.3.2 128-byte FIFO mode
7.3 FIFO operation
7.4 Hardware flow control
When all four of these registers (TXINTLVL, RXINTLVL, FLWCNTH, FLWCNTL) in the
‘first extra feature register set’ are empty (0x00) the transmit and receive trigger levels are
set by FCR[7:4]. In this mode the transmit and receive trigger levels are backward
compatible to the SC16C650B (see
transmit and receive data FIFOs are enabled by the FIFO Control Register bit 0 (FCR[0]).
It should be noted that the user can set the transmit trigger levels by writing to the FCR,
but activation will not take place until EFR[4] is set to a logic 1. The receiver FIFO section
includes a time-out function to ensure data is delivered to the external CPU (see
Section
Table 4.
When either TXINTLVL, RXINTLVL, FLWCNTH or FLWCNTL in the ‘first extra feature
register set’ contains any value other than 0x00, the transmit and receive trigger levels are
set by TXINTLVL and RXINTLVL registers. TXINTLVL sets the trigger levels for the
transmit FIFO, and the transmit trigger levels can be set to any value between 1 and 128
with granularity of 1. RXINTLVL sets the trigger levels for the receive FIFO, the receive
trigger levels can be set to any value between 1 and 128 with granularity of 1.
When the effective FIFO size changes (that is, when FCR[0] toggles or when the
combined content of TXINTLVL, RXINTLVL, FLWCNTH and FLWCNTL changes between
equal and unequal to 0x00), both RX FIFO and TX FIFO will be reset (data in the FIFO will
be lost).
When automatic hardware flow control is enabled, the SC16IS850L monitors the CTS pin
for a remote buffer overflow indication and controls the RTS pin for local buffer overflows.
Automatic hardware flow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[7:6]), and the SC16IS850L will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data
may be sent.
When AFCR1[2] is set to logic 1 then the function of CTS pin is mapped to the DSR pin,
and the function of RTS is mapped to DTR pin. DSR and DTR pins will behave as
described above for CTS and RTS.
FCR[7:6]
00
01
10
11
7.7). Please refer to
Interrupt trigger level and flow control mechanism
FCR[5:4]
00
01
10
11
All information provided in this document is subject to legal disclaimers.
INT pin activation
RX
8
16
24
28
Rev. 1 — 22 July 2011
Table 9
TX
16
8
24
30
Table
and
Table 10
4), and the FIFO sizes are 32 entries. The
Single UART with I
Negate RTS or
send Xoff
8
16
24
28
for the setting of FCR[7:4].
SC16IS850L
2
C-bus/SPI interface
Assert RTS or
send Xon
0
7
15
23
© NXP B.V. 2011. All rights reserved.
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