wm8594seft-v Wolfson Microelectronics plc, wm8594seft-v Datasheet - Page 26

• Manufacturer Part Number: wm8594seft-v
• Description: 24-bit 192khz 2vrms Multi-channel Codec
• Manufacturer: Wolfson Microelectronics plc

WM8594
DIGITAL AUDIO INTERFACE
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Digital audio data is transferred to and from the WM8594 via the digital audio interface. The DACs
have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate
in both master or slave mode. The ADC has independent master clock, bit clock and left/right frame
clock in addition to its data output, and can operate in both master and slave modes.
MASTER MODE
The ADC audio interface requires both a left/right frame clock (ADCLRCLK) and a bit clock
(ADCBCLK). These can be supplied externally (slave mode) or they can be generated internally
(master mode). Selection of master and slave mode is achieved by setting ADC_MSTR in ADC
Control Register 15.
The frequency of ADCLRCLK in master mode is dependent upon the ADC master clock frequency
and the ADC_SR[2:0] bits.
The frequency of ADCBCLK in master mode can be selected by ADC_BCLKDIV[1:0].
The DAC audio interfaces require both left/right frame clocks (DACLRCLK1, DACLRCLK2) and bit
clocks (DACBCLK1, DACBCLK2). These can be supplied externally (slave mode) or they can be
generated internally (master mode). Selection of master and slave mode is achieved by setting
DAC1_MSTR in DAC1 Control Register 4 and DAC2_MSTR in DAC2 Control Register 9.
The frequency of DACLRCLK1 in master mode is dependent upon the DAC1 master clock frequency
and the DAC1_SR[2:0] bits. Similarly the frequency of DACLRCLK2 in master mode is dependent
upon the DAC2 master clock frequency and the DAC2_SR[2:0] bits.
The frequency of DACBCLK1 and DACBCLK2 in master mode can be selected by
DAC1_BCLKDIV[1:0] and DAC2_BCLKDIV[1:0].
DAC1_CTRL2
DAC1_CTRL3
REGISTER
ADDRESS
03h
04h
R3
R4
BIT
2:0
5:3
0
BCLKDIV
SR[2:0]
LABEL
DAC1_
DAC1_
DAC1_
MSTR
[2:0]
DEFAULT
000
000
0
DAC MCLK:LRCLK Ratio
000 = Auto detect
001 = 128fs
010 = 192fs
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = 1152fs
DAC1 BCLK Rate
000 = MCLK / 4
001 = MCLK / 8
010 = 32fs
011 = 64fs
100 = 128fs
All other values of DAC1_BCLKDIV[2:0] are
reserved
DAC1 Master Mode Select
0 = Slave mode, DACBCLK1 and
DACLRCLK1 are inputs to WM8594
1 = Master mode, DACBCLK1 and
DACLRCLK1 are outputs from WM8594
DESCRIPTION
PD Rev 4.1 July 2008
Production Data
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