wm9705seft-v Wolfson Microelectronics plc, wm9705seft-v Datasheet - Page 51

• Manufacturer Part Number: wm9705seft-v
• Description: Multimedia Ac?97 Codec With Integrated Touch Screen Controller
• Manufacturer: Wolfson Microelectronics plc

WM9705
AUXILIARY CONVERSIONS
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Setting PRP[1:0] to 00 will power off the digitiser and and pen down detection. PENDET will not
toggle on pen down.
Provision of the PENDET flag as well as the the AC link wake up procedure allows controllers that
might not be full AC link compliant to still operate in this way, by monitoring the change in state of
PENDET and using that signal as a wake-up flag.
As previously described, auxiliary conversion may be performed by setting the ADR[2-0] address
to the chosen input pin. Two completely dedicated input pins, AUXADC and BMON, and 2 shared
inputs (PHONE, PCBEEP) may be selected as inputs to the ADC. The PHONE and PCBEEP
inputs are normally still available as regular analogue inputs to the mixer path, and as such
present a typical 100k input impedance (with respect to mid-rail). However, in the event that these
analogue inputs are not required, and there is a need to use these inputs as high impedance
auxiliary inputs, then setting bit 6, PHIZ, in register 78h disconnects the internal PHONE and
PCBEEP paths, so making these inputs into high impedance ADC inputs only. The signal paths
from PHONE or PCBEEP to the MIXER are disconnected in this mode.
Inputs to the AUXADC input should never exceed supply rails.
The ADC uses the AVDD1 and AGND1 supplies as it’s references, therefore conversions of
AUXADC or BMON inputs are ratioed to these supplies; if they are inaccurate then the conversion
may be inaccurate in absolute values.
If co-ordinate (COO set) or continuous (CTC set) conversion modes are chosen, then auxiliary
conversions are performed amongst the cycle of screen drives and conversions.
In POLL (POLL set) mode, single auxiliary conversions may be performed. This cycle may be
repeated to allow relatively high conversion rates to be applied to a single channel if required.
In this case, setting the DEL[3-0] value to 15, and the ADR[2-0] value to the required channel will
permanently connect that channel input to the ADC input. In this way maximum cycle time for
conversion may be achieved, by instructing POLL and reading the ADC result on alternate AC link
frames. This gives a maximum conversion rate of 24k samples per second from 1 channel.
Alternatively continuous mode (CTC = ‘1’) may be used to automatically generate conversion
samples a the highest rate. The conversion rate control bits CTR[1-0] will limit this rate unless
DEL[3-0] is set to 15. Then CTR[1-0] sets conversion rates of 1, 2, 4, 6 frames per sample. In this
case up to one conversion is made per AC link frame, giving sample rates of 8, 12, 24 or 48ks/s.
It is recommended that in this case the SLOT method of transferring data is used.
Inputs to the BMON battery monitoring input are allowed to be more positive than the AVdd
supply rail, up to a maximum of 6.5Volts (total). This allows a battery of voltage greater than the
AVdd supply to be monitored by the ADC without need for an external resistive divider. An internal
divide by three consisting of a 20k and a 10k resistor in series, is switched onto the BMON pin
whenever a conversion on this input is requested. Therefore current is consumed from the BMON
input during the battery monitoring conversion process, but not at any other time. A series switch
disconnects the divider from the negative internal supply when conversions are not being
requested. Because of the internal divide by 3, inputs to the BMON pin are therefore converted
with a digital output gain 1/3
The input impedance of the BMON input is 30k to ground WHEN the ADC is sampling, or hi-Z
when it's not. When a BMON sample is requested the ADC samples the battery for a minimum of
two frames. Inherent in this conversion is the delay state, set in register 7h bits 4-7 (DEL [3:0]),
the lowest value of this delay is 0 which will introduce a delay of one frame, thus the minimum
number of 2 frames for a conversion. If the BMON conversion is part of a set of conversions the
delay state set for the series of conversions will be inherited by the BMON conversion. The
minimum time the battery can see the 30k is 512 BCLKs or 41.6 us.
In order to have an equivalent resistance of greater than 1M Ω the battery should be sampled no
more than once every 67 frames.
Effective
_
Input
rd
that of the other AUXADC input
_
R
=
Number
_
of
_
frames
2
_
between
_
samples
×
30000
PD Rev 4.5 July 2008
Production Data
51