a3p250l Actel Corporation, a3p250l Datasheet - Page 107

• Manufacturer Part Number: a3p250l
• Description: Proasic3l Low-power Flash Fpgas With Flash*freeze Technology
• Manufacturer: Actel Corporation

Clock Conditioning Circuits
Table 2-149 • ProASIC3LP CCC/PLL Specification
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable Delay Block
Serial Clock (SCLK) for Dynamic PLL
Input Cycle-to-Cycle Jitter (peak magnitude)
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. This delay is a function of voltage and temperature. See
2. T
3. Maximum value obtained for a Std. speed grade device in worst-case commercial conditions. For specific
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input
junction temperature and voltage supply levels, refer to
clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period
jitter parameter.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
J
= 25°C, V
CCC Electrical Specifications
Timing Characteristics
CC
= 1.2 V
1, 2
3
CCC_OUT
1, 2
1, 2
IN_CCC
OUT_CCC
A dv a n c e v 0. 4
1, 2
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
Table 2-6 on page 2-7
Table 2-6 on page 2-7
Max Peak-to-Peak Period Jitter
Network
1 Global
ProASIC3L DC and Switching Characteristics
0.50%
1.00%
2.50%
0.025
Used
Min.
0.75
48.5
1.2
1.5
for deratings.
for derating values.
External
FB Used
0.75%
1.50%
3.75%
Typ.
270
3.1
Networks
3 Global
0.70%
1.20%
2.75%
15.65
15.65
Max.
Used
250
250
100
300
51.5
6.0
32
1
2
1
Units
MHz
MHz
MHz
ms
ns
ns
%
ns
ps
µs
ns
ns
ns
2 - 95