a3p250l Actel Corporation, a3p250l Datasheet - Page 27

• Manufacturer Part Number: a3p250l
• Description: Proasic3l Low-power Flash Fpgas With Flash*freeze Technology
• Manufacturer: Actel Corporation

1.
If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its
corresponding contribution (P
Combinatorial Cells Contribution—P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
F
P
P
P
P
P
C-CELL
CLK
NET
INPUTS
OUTPUTS
MEMORY
PLL
= P
= (N
is the global clock signal frequency.
N
α
page
N
N
α
page
F
N
α
F
N
α
β
F
N
F
β
F
β
on page
F
CLK
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKOUT
1
2
3
= N
C-CELL
S-CELL
C-CELL
= N
INPUTS
OUTPUTS
BLOCKS
1
1
2
2
DC4
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
is the RAM enable rate for write operations—guidelines are provided in
S-CELL
is the I/O buffer toggle rate—guidelines are provided in
= N
is the I/O buffer toggle rate—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
= P
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
C-CELL
INPUTS
+ P
2-16.
2-16.
AC11
OUTPUTS
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of I/O input buffers used in the design.
AC13
+ N
is the output clock frequency.
is the number of RAM blocks used in the design.
2-16.
*
is the number of I/O output buffers used in the design.
*
* N
AC13
α
C-CELL
α
is the memory read clock frequency.
*F
is the memory write clock frequency.
PLL
1
*
2
BLOCKS
* F
/ 2 * P
CLKOUT
MEMORY
/ 2 * P
α
) *
2
CLKOUT
/ 2 *
α
* F
AC7
AC9
1
NET
/ 2 * P
READ-CLOCK
β
product) to the total PLL contribution.
* F
* F
1
* P
CLK
A dv a n c e v 0. 4
INPUTS
CLK
AC8
OUTPUTS
AC10
C-CELL
* F
*
* F
CLK
β
CLK
2
+ P
1
AC12
* N
BLOCK
ProASIC3L DC and Switching Characteristics
* F
WRITE-CLOCK
Table 2-19 on page
Table 2-19 on page
Table 2-20 on page
*
β
3
Table 2-19 on
Table 2-19 on
Table 2-20
2-16.
2-16.
2-16.
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