hn58x2502fpie Renesas Electronics Corporation., hn58x2502fpie Datasheet - Page 14

no-image

hn58x2502fpie

Manufacturer Part Number
hn58x2502fpie
Description
Serial Peripheral Interface Electrically Erasable And Programmable Read Only Memory
Manufacturer
Renesas Electronics Corporation.
Datasheet
HN58X2502I/HN58X2504I
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q). The most
significant address (A8) should be sent as fifth bit in the instruction byte.
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of
data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued
indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at
any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,
and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
Note:
Address Range Bits
Address bits
Note:
Rev.2.00, Jul.05.2005, page 14 of 20
W
C
D
Q
S
1. Depending on the memory size, as shown in the following table, the most significant address bits are don’t
1. A8 is don’t care on the HN58X2402.
care.
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
Device
0
1
2
Instruction
3
A8
4
A8 to A0
5
High-Z
6
7
A7
8
A6
9 10
HN58X2504I
8-Bit Address
A5
A3
12 13 14 15 16 17 18 19 20 21 22 23
A2
A1
A0
7
6
5
Data Out 1
A7 to A0
4
3
2
1
HN58X2502I
0
7
Data Out 2

Related parts for hn58x2502fpie