gs8160z18b GSI Technology, gs8160z18b Datasheet

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gs8160z18b

Manufacturer Part Number
gs8160z18b
Description
18mb Pipelined And Flow Through Synchronous Nbt Sram
Manufacturer
GSI Technology
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
gs8160z18bGT-150
Manufacturer:
GSI
Quantity:
20 000
Part Number:
gs8160z18bT-150
Quantity:
176
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
Functional Description
The GS8160ZxxBT-xxxV is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.01 5/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
Flow Through
Pipeline
3-1-1-1
2-1-1-1
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
Curr
Curr
Curr
Curr
tCycle
tCycle
Parameter Synopsis
t
(x32/x36)
t
(x32/x36)
KQ
KQ
(x18)
(x18)
1/22
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8160ZxxBT-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, meaning that in addition to the
rising edge triggered registers that capture input signals, the
device incorporates a rising-edge-triggered output register. For
read cycles, pipelined SRAM output data is temporarily stored
by the edge triggered output register during the access cycle
and then released to the output drivers at the next rising edge of
clock.
The GS8160ZxxBT-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
-250
280
330
210
240
3.0
4.0
5.5
5.5
-200
230
270
185
205
3.0
5.0
6.5
6.5
-150
185
210
170
190
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
GS8160ZxxBT-xxxV
© 2004, GSI Technology
250 MHz–150 MHz
1.8 V or 2.5 V V
1.8 V or 2.5 V I/O
Preliminary
DD

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gs8160z18b Summary of contents

Page 1

... KQ 4.0 5.0 tCycle 280 230 Curr (x18) 330 270 Curr (x32/x36) t 5.5 6.5 KQ 5.5 6.5 tCycle 210 185 Curr (x18) 240 205 Curr (x32/x36) 1/22 Preliminary GS8160ZxxBT-xxxV 250 MHz–150 MHz 2.5 V I/O -150 Unit 3.8 ns 6.7 ns 185 mA 210 mA 7.5 ns 7.5 ns 170 mA 190 mA © 2004, GSI Technology DD ...

Page 2

... DDQ Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160Z18BT-xxxV Pinout Top View 2/22 Preliminary GS8160ZxxBT-xxxV ...

Page 3

... DDQ DDQ DDQ DQP 51 A © 2004, GSI Technology ...

Page 4

... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low Core power supply Ground Output driver power supply 4/22 Preliminary GS8160ZxxBT-xxxV ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 2004, GSI Technology ...

Page 5

... GS8160V18/36BT-xxxV NBT SRAM Functional Block Diagram Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Amps Sense Drivers Write 5/22 Preliminary GS8160ZxxBT-xxxV © 2004, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com & determine which bytes will be written. All or none may be activated 6/22 Preliminary GS8160ZxxBT-xxxV , E and E ). Deassertion of any one of the Enable 2 3 © 2004, GSI Technology ...

Page 7

... High-Z 1,2,3, High High High High High High © 2004, GSI Technology Notes 1,10 2 1,2,10 3 1,3, ...

Page 8

... and D represent input command codes ,as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipeline and Flow Through Read/Write Control State Diagram 8/22 Preliminary GS8160ZxxBT-xxxV New Write Burst Write B D n+3 ƒ ƒ © 2004, GSI Technology ...

Page 9

... Transition and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 9/22 Preliminary GS8160ZxxBT-xxxV Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2004, GSI Technology ...

Page 10

... Pipeline and Flow Through Read Write Control State Diagram 10/22 Preliminary GS8160ZxxBT-xxxV R B Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2004, GSI Technology ...

Page 11

... Note: The burst counter wraps to initial state on the 5th clock. 11/22 Preliminary GS8160ZxxBT-xxxV Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2004, GSI Technology ...

Page 12

... Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH DD 12/22 Preliminary GS8160ZxxBT-xxxV 2. The duration of SB tZZR pipelined parts and V on flow DDQ SS © 2004, GSI Technology ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/22 Preliminary GS8160ZxxBT-xxxV Value –0.5 to 4.6 –0 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 1.8 2.0 V 2 © 2004, GSI Technology Unit Notes ...

Page 14

... V V Symbol Test conditions I/O OUT 14/22 Preliminary GS8160ZxxBT-xxxV Typ. Max. Unit V + 0.3 V — DD 0.3*V V — DD Typ. Max. Unit ° ° 20% tKC DD IL Typ. Max. Unit © 2004, GSI Technology Notes 1 1 Notes 2 2 ...

Page 15

... Figure 1 Output Load 1 * 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance Min – ≥ –100 –1 uA OUT DD Min = 1 – 0.4 V DDQ DDQ = 2.375 V 1.7 V — — © 2004, GSI Technology Max 1 uA 100 Max — — 0.4 V 0.4 V ...

Page 16

... GSI Technology Unit ...

Page 17

... GSI Technology ...

Page 18

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Pipeline Mode Timing (NBT) Write B+1 Read C Cont Read D tKL tKL tKH tKH tKC tKC tLZ tS tKQ D(A) D(B) D(B+1) Q(C) tOHZ 18/22 Preliminary GS8160ZxxBT-xxxV Write E Read F Write G Deselect tHZ tKQX Q(D) D(E) Q(F) tOLZ tOE © 2004, GSI Technology D(G) ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Flow Through Mode Timing (NBT) Write B+1 Read C Cont Read D tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 19/22 Preliminary GS8160ZxxBT-xxxV Write E Read F Write tKQX tKQ tHZ tLZ tKQX Q(D) D(E) Q(F) tOLZ tOE © 2004, GSI Technology D(G) ...

Page 20

... Package width and length do not include mold protrusion. Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 20/22 Preliminary GS8160ZxxBT-xxxV E1 E BPR 1999.05.18 © 2004, GSI Technology ...

Page 21

... Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160Z18BT-200IVT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. ...

Page 22

... Types of Changes New Format or Content 8160ZVxxB_r1 8160ZVxxB_r1; 8160ZxxB_V_r_01 Rev: 1.01 5/2006 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • Creation of new datasheet • Changed part numbering due to nomenclature change Content 22/22 Preliminary GS8160ZxxBT-xxxV © 2004, GSI Technology ...

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