hsp50210 Intersil Corporation, hsp50210 Datasheet - Page 17

• Manufacturer Part Number: hsp50210
• Description: Digital Costas Loop
• Manufacturer: Intersil Corporation

The soft decision threshold represents a range of
magnitude values from 0.0 to
to the slicer has a range of 0.0 to
setting should be set to less than 1.0/3 = 0.33. This
avoids saturation. The slicer decisions are output in either
a two’s complement or sign/magnitude format (see Soft
Decision Slicer Configuration Control Register, bit 7: Table
40). The slicer input to output mapping for a range of input
magnitudes is given in Table 7. For example, a negative
input to the slicer whose magnitude is greater than twice
the programmable threshold but less than 3x the threshold
would produce a sign/magnitude output of 110 (BINARY).
The I and Q inputs to the slicer are encoded into 3-bit soft
decisions ISOFT(2-0) and QSOFT(3-0). These signals are
routed to the OUTA(9-4) outputs by the Output
Configuration Control Register Selector bits 0-3 (see
Table 42).
FIGURE 13. OVERLAY OF THE HARD/SOFT DECISION
STRONGER
-FS
FS
‘1’ DECISION
1/2
1/3
1/3
1/2
0
THRESHOLDS ON THE SYMBOL PROBABILITY
DENSITY FUNCTIONS (PDFs) FOR BPSK/QPSK
SIGNALS)
-0.5
‘1’
MSB
MSB
WEAKER
HARD DECISION
THRESHOLD
0.0
3-17
WEAKER
~
MSB-1
MSB-1
MSB-1
MSB-1
0.5. Note: Since the input
‘0’ DECISION
~
‘0’
0.5
1.0, the threshold
THRESHOLD
THRESHOLD
STRONGER
PROBABILITY
FUNCTION
DENSITY
HSP50210
Carrier Phase Error Detector
The Carrier Phase Error is computed by removing the
phase modulation from the phase output of the Cartesian
to Polar Converter. To remove the modulation, the phase
term is rotated and multiplied (modulo 2 ) to fold the Phase
Error into an arc centered about 0
whole plane, as shown in Figure 14. The phase rotation is
performed by adding a 4-bit two’s complement phase offset
(resolution 22.5
The multiplication is performed by left shifting the result
from 0-3 positions with the MSB’s discarded and zeros
inserted into the LSB’s. For example, Carrier Phase Error
produces I/Q constellation points which are rotated from
the expected constellation points as shown in Figure 14. By
adding an offset of 45
by 4 (left shift by two positions) the phase modulation is
removed, and the error is folded into a 90
0
implying the vertical axis is 22.5
The phase offset and shift factors required for different PSK
orders is given in Table 8. Configuration of the Carrier
Phase Error Detector is done via the Carrier Phase Error
Detector Control Register, bits 0-5, (see Table 17). The
Phase Error term may be selected for output via the Output
Selector Configuration Control Register, bits 0-3 (see
Table 42).
o
. The left axis represents a decision boundary of 45
+
+
+
+
-
-
-
-
TABLE 7. SLICER INPUT TO OUTPUT MAPPING
SLICER INPUT MAGNITUDE
>
>
>
>
>
>
o
) to the 4 MSBs of the 8-bit phase term.
RELATIVE TO
o
(0010 0000 binary) and multiplying
>
>
<
<
>
>
o
>
<
<
<
<
>
o
as shown in Figure 14.
but encompasses the
o
011
010
001
000
100
101
110
111
arc centered at
011
010
001
000
111
110
101
100
o
C,